Three-wire-line vertical interconnect structure for multilevel substrates
    1.
    发明授权
    Three-wire-line vertical interconnect structure for multilevel substrates 失效
    用于多层基板的三线垂直互连结构

    公开(公告)号:US5644277A

    公开(公告)日:1997-07-01

    申请号:US553946

    申请日:1995-11-06

    摘要: A vertical interconnect structure comprising a three-wire-line transmission line structure for providing electrical continuity between different levels of a multilevel substrate. The present invention provides a means for transferring power between various levels of the substrate without introducing excessive additional RE losses. First and second coplanar transmission line structures are disposed on first and second surfaces of the substrate. A vertical interconnect structure is disposed in the multilevel RF substrate and is coupled between the first and second transmission line structures. The vertical interconnect structure comprises three conductors having predetermined cross-sectional dimensions and predetermined separations therebetween that are adapted to transfer RE power between the first and second transmission line structures. In a completed electronic circuit employing the present invention, an electronic device is electrically coupled between two coplanar transmission line structures disposed on one surface of the substrate, and the vertical interconnect structure couples power to the electronic circuit by way of the coplanar transmission line structure disposed another surface of the substrate. The impedance of the vertical interconnect structure is determined by the relative dimensions of the three conductors and their relative separations. The three-wire-line transmission line structure supports a highly desirable TEM mode of energy propagation. The present invention is relatively easy to fabricate, in that vertical wires having a circular geometry are easily accommodated as part of the fabrication process for the substrate. The present invention provides for relatively low loss, because of the nature of the currents that flow on the conductors. The propagation characteristics are well-understood, and the vertical interconnect structure supports a highly desirable TEM mode of energy propagation.

    摘要翻译: 一种垂直互连结构,包括用于在多层基板的不同层次之间提供电连续性的三线制传输线结构。 本发明提供了一种在不引入额外的额外RE损耗的情况下在不同层次的衬底之间传递功率的装置。 第一和第二共面传输线结构设置在基板的第一和第二表面上。 垂直互连结构设置在多电平RF衬底中并耦合在第一和第二传输线结构之间。 垂直互连结构包括具有预定横截面尺寸和其间的预定间隔的三个导体,其适于在第一和第二传输线结构之间传送RE功率。 在使用本发明的完整的电子电路中,电子器件电耦合在设置在衬底的一个表面上的两个共面传输线结构之间,并且垂直互连结构通过所设置的共面传输线结构将功率耦合到电子电路 衬底的另一表面。 垂直互连结构的阻抗由三根导线的相对尺寸及其相对间距决定。 三线制传输线结构支持高度可取的TEM模式的能量传播。 本发明相对容易制造,因为具有圆形几何形状的垂直导线容易被容纳作为衬底制造工艺的一部分。 由于在导体上流动的电流的性质,本发明提供相对较低的损耗。 传播特性是很好理解的,垂直互连结构支持高度期望的TEM模式的能量传播。

    Light-weight modular low-level reconfigurable beamformer for array antennas
    2.
    发明授权
    Light-weight modular low-level reconfigurable beamformer for array antennas 有权
    阵列天线的轻量级模块化低级可重构波束形成器

    公开(公告)号:US06246364B1

    公开(公告)日:2001-06-12

    申请号:US09336224

    申请日:1999-06-18

    IPC分类号: H01Q324

    摘要: A method and apparatus for forming satellite transmission beams are disclosed. A beamforming network in accordance with the present invention comprises an array of antennas and primary and secondary dividing networks. The array of antennas comprises at least a first subarray having a first number of elements and a second subarray having a second number of elements. The primary dividing network divides a beam signal into a plurality of panel signals, wherein a number of panel signals is substantially equal to a number of subarrays. The secondary dividing network divides a first panel signal into a first plurality of element signals substantially equal in number to the first number of elements and for dividing a second panel signal into a second plurality of element signals substantially equal in number to the second number of elements.

    摘要翻译: 公开了一种用于形成卫星传输梁的方法和装置。 根据本发明的波束成形网络包括天线阵列和初级和次级分配网络。 天线阵列至少包括具有第一数量的元件的第一子阵列和具有第二数量的元件的第二子阵列。 主分割网络将波束信号分成多个面板信号,其中多个面板信号基本上等于多个子阵列。 次级分配网络将第一面板信号划分为与第一数量的元件基本相等的第一多个元件信号,并将第二面板信号分成与第二数量的元件基本相等的第二多个元件信号 。

    Multi-layer circuit board and semiconductor flip chip connection
    3.
    发明授权
    Multi-layer circuit board and semiconductor flip chip connection 失效
    多层电路板和半导体倒装芯片连接

    公开(公告)号:US5768109A

    公开(公告)日:1998-06-16

    申请号:US681136

    申请日:1996-07-22

    摘要: A multi-layer circuit board (11) has a cofired ceramic with a configuration of circuit traces (27) extending though differing layers of the multi-layer circuit board (11) to facilitate mountable conductive contact with semiconductor flip chips (13). Via holes (23) are precisely formed in the multi-layer circuit board (11) and are filled with solder or conductive epoxy. Semiconductor chips (13) have an array of metallic posts (19) alignable with the holes (23) and are mounted upon the upper surface of the multi-layer circuit board (11) in plug fashion. An aperture (25) may be formed in multi-layer circuit board (11) directly below each semiconductor chip (13) for protection of the circuitry on semiconductor chip (13) from contact with multi-layer circuit board (11). The via holes (23) and transmission line structure of the circuit board (11) are precisely formed to achieve a desired characteristic impedance.

    摘要翻译: 多层电路板(11)具有共烧陶瓷,​​其具有通过多层电路板(11)的不同层延伸的电路迹线(27)的结构,以便于与半导体倒装芯片(13)的可安装的导电接触。 通孔(23)精确地形成在多层电路板(11)中并填充有焊​​料或导电环氧树脂。 半导体芯片(13)具有与孔(23)对准的金属柱(19)的阵列,并且以插头方式安装在多层电路板(11)的上表面上。 可以在每个半导体芯片(13)的正下方的多层电路板(11)中形成孔(25),以保护半导体芯片(13)上的电路与多层电路板(11)的接触。 通孔(23)和电路板(11)的传输线结构被精确地形成以实现期望的特性阻抗。