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公开(公告)号：US09054178B2
公开(公告)日：2015-06-09
申请号：US14174822
申请日：2014-02-06
申请人： Mark T. Bohr , Tahir Ghani , Nadia M. Rahhai-Orabi , Subhash M. Joshi , Joseph M. Steigerwald , Jason W. Klaus , Jack Hwang , Ryan Mackiewicz
发明人： Mark T. Bohr , Tahir Ghani , Nadia M. Rahhai-Orabi , Subhash M. Joshi , Joseph M. Steigerwald , Jason W. Klaus , Jack Hwang , Ryan Mackiewicz
IPC分类号： H01L29/417 , H01L29/78 , H01L29/06 , H01L21/768 , H01L29/66 , H01L29/51 , H01L29/49
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/28229 , H01L21/28255 , H01L21/283 , H01L21/28562 , H01L21/31105 , H01L21/76802 , H01L21/76831 , H01L21/76849 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L29/0847 , H01L29/16 , H01L29/42364 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/78 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。
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公开(公告)号：US20140002976A1
公开(公告)日：2014-01-02
申请号：US13997974
申请日：2011-11-10
IPC分类号： H01L49/02 , H01L27/108 , G06F1/16
CPC分类号： H01L28/40 , G06F1/16 , H01L27/108 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： A capacitor-over-bitline structure includes a bottom electrode that has an open vessel form factor. The bottom-electrode form factor includes a floor, rectilinear sidewalls, and a rim that defines the topmost feature. A capacitor dielectric film contacts and covers the floor, the sidewalls, and the rim. A top electrode has a convex form factor that complements the concave bottom-electrode form factor. A process of forming the capacitor-over-bitline structure by spinning on a reflowable sacrificial material such as an oxide that covers both logic and memory portions of a semiconductive device, followed by a polish-back process and a recessing etch of the bottom electrode.
摘要翻译： 电容器 - 位线结构包括具有开放容器外形的底部电极。 底部电极形状因子包括底板，直线侧壁和限定最顶端特征的边缘。 电容器电介质膜接触并覆盖地板，侧壁和边缘。 顶部电极具有补充凹底电极形状因子的凸形形状因子。 通过在可覆盖的牺牲材料（例如覆盖半导体器件的逻辑和存储器部分的氧化物）上旋转形成电容器 - 位线结构的过程，接着是底部电极的抛光处理和凹陷蚀刻。
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公开(公告)号：US20110147851A1
公开(公告)日：2011-06-23
申请号：US12641497
申请日：2009-12-18
申请人： Christopher D. Thomas , Joseph M. Steigerwald , Timothy E. Glassman , Kyoung H. Kim , Dan S. Lavric , Michael Ollinger , M. N. Perez-Paz
发明人： Christopher D. Thomas , Joseph M. Steigerwald , Timothy E. Glassman , Kyoung H. Kim , Dan S. Lavric , Michael Ollinger , M. N. Perez-Paz
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823821 , H01L21/28088 , H01L21/823828 , H01L21/823842 , H01L29/4966
摘要： A semiconductor device comprises a substrate, a channel region, and a gate formed in association with the channel region. In one exemplary embodiment, the gate comprises a first material that is formed void free on an interior surface of a gate trench of the gate. A width of the gate trench comprises between about 8 nm and about 65 nm. The gate comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal. In another exemplary embodiment, the gate further comprises a second material formed void free on an interior surface of the first material and comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal.
摘要翻译： 半导体器件包括与沟道区域相关联地形成的衬底，沟道区域和栅极。 在一个示例性实施例中，栅极包括在栅极的栅极沟槽的内表面上无空隙形成的第一材料。 栅极沟槽的宽度包括约8nm至约65nm。 栅极包括与碳，铝或氮合金或其组合的过渡金属，以形成过渡金属的碳化物，氮化物或碳氮化物或其组合。 在另一个示例性实施例中，门还包括在第一材料的内表面上形成为空隙的第二材料，并且包括与碳，铝或氮或其组合合金化的过渡金属，以形成碳化物，氮化物或 氮化碳或其组合。
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公开(公告)号：US20110147831A1
公开(公告)日：2011-06-23
申请号：US12646678
申请日：2009-12-23
CPC分类号： H01L21/823842 , H01L21/823431 , H01L21/82345 , H01L21/823821 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： An exemplary embodiment of a method for forming a gate for a planar-type or a finFET-type transistor comprises forming a gate trench that includes an interior surface. A first work-function metal is formed on the interior surface of the gate trench, and a low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. Another exemplary embodiment provides that a second work-function metal is formed on the first work-function metal, and then the low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof.
摘要翻译： 用于形成平面型或finFET型晶体管的栅极的方法的示例性实施例包括形成包括内表面的栅极沟槽。 第一工作功能金属形成在栅极沟槽的内表面上，并且使用化学气相沉积（CVD）技术或原子层沉积（ALD）沉积在第一功函数金属上的低电阻率材料， 技术或其组合。 另一示例性实施例提供了在第一工作功能金属上形成第二功函数金属，然后使用化学气相沉积（CVD）技术将低电阻率材料沉积在第一功函数金属上，或者使用原子 层沉积（ALD）技术或其组合。
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公开(公告)号：US07052996B2
公开(公告)日：2006-05-30
申请号：US10722801
申请日：2003-11-26
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： C25F3/02 , H01L21/32125 , Y10S438/959
摘要： An electropolish process may remove a conductive film from a semiconductor wafer. An electropolish apparatus having a pad over a platen may make surface-to-surface electrical contact with the conductive film of the wafer across the entire surface of the pad and the conductive film on the wafer. An electric field may be applied through openings in the pad and electrodes which receive potential by feedthroughs that extend through the platen to those electrodes. The electrodes in the feedthroughs may be electrically isolated from the pad and the platen. As a result, more uniform application of electrical potential across the surface to be polished may be achieved in some embodiments.
摘要翻译： 电解抛光工艺可以从半导体晶片去除导电膜。 具有在压板上的焊盘的电抛光装置可以在晶片的整个表面和晶片上的导电膜之间与晶片的导电膜进行表面 - 表面的电接触。 可以通过焊盘中的开口施加电场，并且通过穿过压板的那些电极接收电位的电极。 馈通中的电极可以与焊盘和压板电隔离。 结果，在一些实施例中可以实现在待抛光表面上更均匀地施加电位。
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公开(公告)号：US6103625A
公开(公告)日：2000-08-15
申请号：US1549
申请日：1997-12-31
IPC分类号： H01L21/321 , H01L21/768 , H01L21/302
CPC分类号： H01L21/3212 , H01L21/76807 , H01L21/7684
摘要： The present invention describes a method of forming an interconnect structure. An insulating layer is formed, and then an opening is formed in the insulating layer. Next, a conductive layer is formed over the insulating layer and in the opening. A polishing stop layer is then formed over the conductive layer. The polishing stop layer and the conductive layer are then polished; however, the polishing stop layer is polished at a slower rate than the conductive layer.
摘要翻译： 本发明描述了形成互连结构的方法。 形成绝缘层，然后在绝缘层中形成开口。 接下来，在绝缘层和开口中形成导电层。 然后在导电层上形成抛光停止层。 然后研磨抛光停止层和导电层; 然而，抛光停止层以比导电层更慢的速度被抛光。
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7.发明授权Systems for performing chemical mechanical planarization and process for conducting same 失效用于执行化学机械平面化的系统和用于进行其的处理
公开(公告)号：US5637185A
公开(公告)日：1997-06-10
申请号：US413487
申请日：1995-03-30
IPC分类号： B24B37/005 , B24B49/02 , B24B1/00 , B24B37/00
CPC分类号： B24B37/005 , B24B49/02
摘要： A system for performing chemical mechanical planarization for a semiconductor wafer includes a chemical mechanical polishing system including a chemical mechanical polishing slurry. The system also includes a device for measuring the electrochemical potential of the slurry during processing which is electrically connected to the slurry, and a device for detecting the end point of the process, based upon the electrochemical potential of the slurry, which is responsive to the electrochemical potential measuring device. Accurate in situ control of a chemical mechanical polishing process is thereby provided.
摘要翻译： 用于对半导体晶片执行化学机械平面化的系统包括包括化学机械抛光浆料的化学机械抛光系统。 该系统还包括一种用于在处理期间测量浆料的电化学电位的装置，其与浆料电连接，以及用于基于浆料的电化学电位检测该工艺的终点的装置，其响应于 电化学电位测量装置。 从而提供了化学机械抛光工艺的准确原位控制。
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8.发明申请公开(公告)号：US20150171218A1
公开(公告)日：2015-06-18
申请号：US14108265
申请日：2013-12-16
申请人： Joseph M. Steigerwald , Tahir Ghani , Jenny Hu , Ian R. C. Post
发明人： Joseph M. Steigerwald , Tahir Ghani , Jenny Hu , Ian R. C. Post
IPC分类号： H01L29/78 , H01L29/423 , H01L21/28 , H01L29/66
CPC分类号： H01L29/7831 , H01L21/28114 , H01L21/823431 , H01L21/82345 , H01L21/823456 , H01L27/0886 , H01L29/42372 , H01L29/42376 , H01L29/4908 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66484 , H01L29/66772 , H01L29/66795 , H01L29/7855 , H01L29/7856 , H01L29/78645
摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例描述了多阈值电压装置及相关联的技术和配置。 在一个实施例中，一种装置包括半导体衬底，设置在半导体衬底上的沟道体，具有与沟道本体耦合的第一厚度的第一栅电极和具有与沟道本体耦合的第二厚度的第二栅电极，其中， 第一厚度大于第二厚度。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20140264679A1
公开(公告)日：2014-09-18
申请号：US13994716
申请日：2013-03-15
申请人： Kevin J. Lee , Tahir Ghani , Joseph M. Steigerwald , John H. Epple , Yih Wang
发明人： Kevin J. Lee , Tahir Ghani , Joseph M. Steigerwald , John H. Epple , Yih Wang
CPC分类号： H01L43/12 , G11C11/161 , H01L27/222 , H01L27/226 , H01L43/08
摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.
摘要翻译： 实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上部MTJ层，较低MTJ层和直接接触上层MTJ层和下层MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。 另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。 在一个实施例中，第一和第二ILD直接彼此接触。 本文描述了其它实施例。
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10.发明申请公开(公告)号：US20140001598A1
公开(公告)日：2014-01-02
申请号：US13977550
申请日：2011-12-21
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , C23C16/0281 , C23C16/045 , C23C16/32 , C23C16/45525
摘要： Atomic layer deposition (ALD) of TaAlC for capacitor integration is generally described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in at least one of the dielectric layers, the MIM capacitor includes an electrode having a conformal layer of TaAlC and the MIM capacitor is electrically coupled to one or more of the semiconductor devices. Other embodiments are also disclosed and claimed.
摘要翻译： 通常描述用于电容器集成的TaAlC的原子层沉积（ALD）。 例如，半导体结构包括设置在基板中或上方的多个半导体器件。 一个或多个电介质层设置在多个半导体器件的上方。 金属绝缘体金属（MIM）电容器设置在至少一个电介质层中，MIM电容器包括具有保形层TaAlC的电极，并且MIM电容器电耦合到一个或多个半导体器件。 还公开并要求保护其他实施例。
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