公开(公告)号：US08736064B2

公开(公告)日：2014-05-27

申请号：US12941511

申请日：2010-11-08

申请人： Hideki Kotake ,  Kiyoshi Hyodo ,  Inetaro Kurosawa ,  Yukio Hashimoto ,  Toku Yoshino ,  Tomoo Iijima

发明人： Hideki Kotake ,  Kiyoshi Hyodo ,  Inetaro Kurosawa ,  Yukio Hashimoto ,  Toku Yoshino ,  Tomoo Iijima

IPC分类号： H01L23/522

CPC分类号： H05K3/4038 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/20 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4647 ,  H05K3/4658 ,  H05K2201/0379 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1536 ,  H01L2924/00014 ,  H01L2924/00012

摘要： An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.

摘要翻译： 提供互连元件。 单片电介质元件具有第一暴露的主表面，从第一主表面向内延伸的多个第一凹槽和远离第一主表面的第二暴露的主表面，从第二主表面向内延伸的多个第二凹槽。 多个第一金属互连图案被嵌入在多个第一凹部中并沿着第一主表面沿一个或多个方向延伸。 多个第二金属互连图案被嵌入在多个第二凹部中并沿着第二主表面沿一个或多个方向延伸。 多个非中空金属柱在多个第一金属互连图案中的至少一些和多个第二金属互连图案中的至少一些之间延伸穿过介质元件。

公开(公告)号：US08112881B2

公开(公告)日：2012-02-14

申请号：US11720711

申请日：2005-09-29

申请人： Kazuhiro Shimizu ,  Masanobu Yagi ,  Kenichiro Hanamura ,  Mitsuyuki Takayasu ,  Kiyoe Nagai ,  Tomoo Iijima

发明人： Kazuhiro Shimizu ,  Masanobu Yagi ,  Kenichiro Hanamura ,  Mitsuyuki Takayasu ,  Kiyoe Nagai ,  Tomoo Iijima

IPC分类号： H05K3/20

CPC分类号： H05K3/4038 ,  B32B37/26 ,  B32B2457/08 ,  H05K3/022 ,  H05K3/06 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1461 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49163

摘要： A process for manufacturing a multilayer wiring board including the steps of forming an insulating layer on a base provided with a bump for interlayer connection, bonding a copper foil onto the insulating layer by a thermocompression bonding by sandwiching the copper foil between stainless steel plates, and patterning the copper foil, in which a metal foil is interposed at least between each of the stainless plates and the copper foil at the time of the thermocompression bonding. At this time, a mold release layer is formed on a surface of the metal foil to be imposed. Thus, such a multilayer wiring board can be manufactured that prevents sticking of a product after molding (cementing of the copper foil) and excels in dimensional stability without occurrence of wrinkling and ruggedness.

摘要翻译： 一种多层布线板的制造方法，包括以下步骤：在设置有用于层间连接的凸块的基底上形成绝缘层，通过将铜箔夹在不锈钢板之间通过热压接将铜箔接合到绝缘层上;以及 在热压接时，至少在每个不锈钢板和铜箔之间插入金属箔的铜箔图案化。 此时，在要施加的金属箔的表面上形成脱模层。 因此，可以制造这样的多层布线板，其防止成型后的产品粘附（铜箔的粘合），并且尺寸稳定性优异，而不会发生起皱和粗糙。

公开(公告)号：US07546681B2

公开(公告)日：2009-06-16

申请号：US11487747

申请日：2006-07-17

申请人： Tomoo Iijima ,  Masayuki Ohsawa

发明人： Tomoo Iijima ,  Masayuki Ohsawa

IPC分类号： H05K3/36

CPC分类号： H05K3/4647 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/06 ,  H05K3/062 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/0384 ,  H05K2203/041 ,  H05K2203/0733 ,  H05K2203/1189 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49137 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

摘要： A method of making a microelectronic element includes making a connection component by providing a metal layer having a top surface and a bottom surface, providing a dielectric layer over the top surface of the metal layer and forming openings in the dielectric layer to expose portions of the top surface of the metal layer. The method includes providing conductive elements atop the dielectric layer, at least some of the conductive elements extending through the openings in the dielectric layer and being in contact with the metal layer, and plating first conductive protrusions atop the at least some of the conductive elements extending through the openings in the dielectric layer, the first conductive protrusions extending away from the metal layer. The method includes selectively removing portions of the metal layer from the bottom surface of the metal layer to form second conductive protrusions that extend away from the first conductive protrusions. At least some of the first and second conductive protrusions are electrically interconnected with one another.

摘要翻译： 制造微电子元件的方法包括通过提供具有顶表面和底表面的金属层来制造连接部件，在金属层的顶表面上提供介电层，并在电介质层中形成开口以暴露部分 金属层的顶面。 该方法包括在电介质层的顶部提供导电元件，至少一些导电元件延伸穿过电介质层中的开口并与金属层接触，并且在至少一些导电元件延伸的顶部上镀覆第一导电突起 通过电介质层中的开口，第一导电突出部远离金属层延伸。 该方法包括从金属层的底表面选择性地去除金属层的部分，以形成远离第一导电突起延伸的第二导电突起。 第一和第二导电突起中的至少一些彼此电互连。

公开(公告)号：US20050224256A1

公开(公告)日：2005-10-13

申请号：US11085108

申请日：2005-03-22

申请人： Kenji Osawa ,  Masayuki Osawa ,  Tomokazu Shimada ,  Kimitaka Endo ,  Tomoo Iijima

发明人： Kenji Osawa ,  Masayuki Osawa ,  Tomokazu Shimada ,  Kimitaka Endo ,  Tomoo Iijima

IPC分类号： H01L21/4763 ,  H01L21/48 ,  H01L21/60 ,  H01L23/50 ,  H05K1/11 ,  H05K1/16 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC分类号： H05K3/4614 ,  H01L2924/0002 ,  H05K3/423 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/10378 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1152 ,  H01L2924/00

摘要： To increase the dimensional accuracy of an interlayer member used for producing a multilayer wiring board which is inserted between two wiring layers to establish interlayer insulation and interlayer electrical connection between the wiring layers, to thereby increase a layout density. A mask film is formed on a main surface of a sheet-like carrier layer. A metal column for interlayer connection is formed on the main surface of the carrier layer by plating a copper using the mask film as a mask. The mask film is removed. An interlayer insulating layer and a protective sheet are laminated on the main surface of the carrier layer in such a manner that the metal column for interlayer connection penetrates them. The interlayer insulating layer and the protective sheet are polished until the upper surface of the metal column for interlayer connection is exposed. Then, the carrier layer is removed. Furthermore, the protective sheet is removed.

摘要翻译： 为了提高用于制造插入在两个布线层之间的多层布线板的层间构件的尺寸精度，以​​建立布线层之间的层间绝缘和层间电连接，从而增加布局密度。 在片状载体层的主表面上形成掩模膜。 通过使用掩模膜作为掩模将铜电镀形成在载体层的主表面上的用于层间连接的金属柱。 去除掩模膜。 层间绝缘层和保护片层叠在载体层的主表面上，使得用于层间连接的金属柱穿透它们。 抛光层间绝缘层和保护片，直到露出用于层间连接的金属柱的上表面。 然后，移除载体层。 此外，去除保护片。

公开(公告)号：US06528874B1

公开(公告)日：2003-03-04

申请号：US09685799

申请日：2000-10-11

申请人： Tomoo Iijima ,  Masayuki Ohsawa

发明人： Tomoo Iijima ,  Masayuki Ohsawa

IPC分类号： H01L2312

CPC分类号： H05K3/4647 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/06 ,  H05K3/062 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/0384 ,  H05K2203/041 ,  H05K2203/0733 ,  H05K2203/1189 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49137 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

摘要： The present invention prepares a member having a conductor-circuit-forming copper foil 21 formed on a protrusion-forming copper layer 23 via an etching-barrier layer 22 formed of a different metal. Etching is selectively performed for the protrusion-forming copper foil 21 by using etchant that does not etch the etching-barrier layer, and protrusions 25 are thereby formed. Then, the etching-barrier layer 22 is removed using etchant that does not etch the copper foil 23 and using the protrusions as masks. An interlayer-insulating layer 27 is formed on a surface of the copper foil 23, on which the protrusions 25 are formed, so that the protrusions are connected to the conductor circuit. Thereby, heights of the protrusions are uniformed, and the reliability of connections can be improved.

摘要翻译： 本发明通过由不同金属形成的蚀刻阻挡层22制备具有形成在突起形成铜层23上的导体电路形成铜箔21的部件。 通过使用不蚀刻蚀刻阻挡层的蚀刻剂来选择性地对突起形成铜箔21进行蚀刻，从而形成突起25。 然后，使用不蚀刻铜箔23并使用突起作为掩模的蚀刻剂去除蚀刻阻挡层22。 在铜箔23的形成有突起25的表面上形成层间绝缘层27，使得突起与导体电路连接。 由此，突起的高度均匀，可以提高连接的可靠性。

公开(公告)号：US06372620B1

公开(公告)日：2002-04-16

申请号：US09253441

申请日：1999-02-19

申请人： Kenji Oosawa ,  Tomoo Iijima ,  Hidetoshi Kusano

发明人： Kenji Oosawa ,  Tomoo Iijima ,  Hidetoshi Kusano

IPC分类号： H01L2144

CPC分类号： H05K3/4007 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/3025 ,  H05K3/205 ,  H05K3/243 ,  H01L2924/00014 ,  H01L2924/00

摘要： By adopting an electrolytic plating method in forming the bump, the drawbacks of the conventional electrolytic plating method should be avoided. For example, the necessity of adopting a lead wiring for each wiring or the like should be eliminated. On the surface of a metal base, a resist film (first resist film) having a negative pattern for forming a wiring film and a resist film (second resist film) having a negative pattern for forming the bump or the pad is formed. By using these films as masks, electrolyic plating of a bump material film is conducted to form the bump. Subsequently, after only the second film is removed. By using the first resist film as a mask, electrolytic plating is then conducted to form a wiring film.

摘要翻译： 通过在形成凸块时采用电解电镀方法，应避免常规电解电镀方法的缺点。 例如，应该消除对每个布线等采用引线的必要性。 在金属基体的表面上，形成具有用于形成布线膜的负图案的抗蚀剂膜（第一抗蚀剂膜）和具有用于形成凸块或焊盘的负图案的抗蚀剂膜（第二抗蚀剂膜）。 通过使用这些膜作为掩模，进行凸块材料膜的电镀以形成凸块。 随后，仅仅第二个膜被去除之后。 通过使用第一抗蚀剂膜作为掩模，然后进行电镀以形成布线膜。

公开(公告)号：US20070209199A1

公开(公告)日：2007-09-13

申请号：US11784810

申请日：2007-04-10

申请人： Tomoo Iijima ,  Masayuki Ohsawa

发明人： Tomoo Iijima ,  Masayuki Ohsawa

IPC分类号： H05K3/36

CPC分类号： H05K3/4647 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/06 ,  H05K3/062 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/0384 ,  H05K2203/041 ,  H05K2203/0733 ,  H05K2203/1189 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49137 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

摘要： A method of making a microelectronic assembly includes providing a conductive metal layer having a first surface and a second surface, and etching the first surface of the conductive metal layer to form conductive protrusions, whereby after the etching step, the second surface of the conductive metal layer defines a substantially flat, continuous surface. The method includes juxtaposing a layer of an insulating material with tips of the conductive protrusions, and pressing the conductive protrusions through the layer of an insulating material so that the tips of the conductive protrusions are accessible at a first surface of the layer of an insulating material. In certain embodiments, the method may include after the pressing step, etching the second surface of the conductive metal layer to form conductive traces that are electrically interconnected with the conductive protrusions. The layer of an insulating material may be heated before the pressing step so as to soften the layer of an insulating material during the pressing step. The layer of an insulating material may be cooled to an ambient temperature after the pressing step. A microelectronic element, such as a semiconductor chip, is electrically interconnected with said conductive protrusions. The microelectronic assembly may also be electrically interconnected with a microelectronic structure having one or more layers, such as a multi-level microelectronic structure.

摘要翻译： 制造微电子组件的方法包括提供具有第一表面和第二表面的导电金属层，并且蚀刻导电金属层的第一表面以形成导电突起，由此在蚀刻步骤之后，导电金属的第二表面 层限定基本平坦的连续表面。 该方法包括将绝缘材料层与导电突起的尖端并置，并且通过绝缘材料层压住导电突起，使得导电突起的顶端在绝缘材料层的第一表面可接近 。 在某些实施例中，该方法可以包括在压制步骤之后，蚀刻导电金属层的第二表面以形成与导电突起电互连的导电迹线。 可以在压制步骤之前加热绝缘材料层，以在压制步骤期间软化绝缘材料层。 在压制步骤之后，可以将绝缘材料层冷却至环境温度。 诸如半导体芯片的微电子元件与所述导电突起电互连。 微电子组件也可以与具有一层或多层的微电子结构电互连，例如多级微电子结构。

公开(公告)号：US20050097727A1

公开(公告)日：2005-05-12

申请号：US10450844

申请日：2002-03-27

申请人： Tomoo Iijima ,  Yoshiro Kato ,  Hiroshi Odaira ,  Masayuki Ohsawa ,  Inetaro Kurosawa ,  Kazuo Sakuma ,  Toshihiko Asano ,  Kimitaka Endo

发明人： Tomoo Iijima ,  Yoshiro Kato ,  Hiroshi Odaira ,  Masayuki Ohsawa ,  Inetaro Kurosawa ,  Kazuo Sakuma ,  Toshihiko Asano ,  Kimitaka Endo

IPC分类号： B24B1/00 ,  B24B7/22 ,  B24B37/04 ,  H05K3/06 ,  H05K3/40 ,  H05K3/46 ,  H01R3/00 ,  B23P19/00

CPC分类号： H05K3/4614 ,  B24B1/00 ,  B24B7/228 ,  B24B37/04 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2203/0143 ,  H05K2203/025 ,  H05K2203/0384 ,  H05K2203/061 ,  Y10T29/5313

摘要： A plurality of multi-layer metal plates (1) each being composed of a bump forming metal layer (2), an etching stop layer (3), and a wiring film forming metal layer (4), and in which a wiring film (4a) is formed from the wiring film forming metal layer and a bump 2a is formed from the bump forming metal layer are prepared, and on a bump forming surface of a multi-layer metal plate, a wiring film of another multi-layer metal plate is overlapped. Such lamination process is repeated in succession for multi-layering. In addition, a polishing machine for multi-layer wiring board (11a) which includes metal plate holding means (13) for holding a metal plate (1a), cutter holding means (25) for holding a cutter (26) above the metal plate, height adjustment mechanism (20) for adjusting the height of the cutter holding means, and cutter parallel moving mechanism (15) for relatively moving the cutter holding means in parallel to the surface of the metal plate is used to conduct polishing.

摘要翻译： 多个多层金属板（1）各自由凸块形成金属层（2），蚀刻停止层（3）和布线膜形成金属层（4）构成，其中布线膜 由凸极形成金属层形成由布线膜形成金属层形成的凸块2a，并且在多层金属板的凸块形成表面上形成另一多层的布线膜 金属板重叠。 这样的层压方法被连续重复进行多层。 另外，包括用于保持金属板（1a）的金属板保持装置（13）的多层布线板（11a）的抛光机，用于将切割器（26）保持在其上方的切割器保持装置（25） 金属板，用于调节刀具保持装置的高度的高度调节机构（20）以及用于使刀具保持装置平行于金属板的表面相对移动的刀具平行移动机构（15）进行抛光。

公开(公告)号：US06782610B1

公开(公告)日：2004-08-31

申请号：US09466895

申请日：1999-12-20

申请人： Tomoo Iijima ,  Masayuki Oosawa ,  Shigeo Hirade

发明人： Tomoo Iijima ,  Masayuki Oosawa ,  Shigeo Hirade

IPC分类号： H01R4300

CPC分类号： H01L21/6835 ,  H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8547 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3651 ,  H05K3/062 ,  H05K3/205 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a method for fabricating a wiring substrate by forming an insulating film on a metal base having openings on the metal base at positions corresponding to metal bumps to be formed later; forming at least one layer of wiring on the base made of a metal through the insulating film, the layer of wiring having a wring film formed thereon by electroplating; and selectively etching the base. The insulating film can be a liquid photosensitive polyamide, the wiring layer can be copper and the wiring film can be a conductive layer selected from the group consisting of Ni-P and Ni. In the present invention, the wiring layer can be formed through the insulating film in contact with the metal base at the openings in the insulating film and in contact with the insulating film where there are no openings in the insulating film.

摘要翻译： 本发明涉及一种制造布线基板的方法，该方法通过在金属基底上形成绝缘膜，该金属基体在金属基体上相应于稍后形成的金属凸块的位置上具有开口; 通过绝缘膜在由金属制成的基底上形成至少一层布线，该布线层具有通过电镀形成在其上的缠绕膜; 并选择性地蚀刻基底。 绝缘膜可以是液体感光性聚酰胺，布线层可以是铜，布线膜可以是选自Ni-P和Ni的导电层。 在本发明中，可以通过在绝缘膜的开口处与金属基体接触的绝缘膜形成布线层，并且与绝缘膜中没有开口的绝缘膜接触。

公开(公告)号：US06617236B2

公开(公告)日：2003-09-09

申请号：US10072351

申请日：2002-02-07

申请人： Kenji Oosawa ,  Tomoo Iijima ,  Hidetoshi Kusano

发明人： Kenji Oosawa ,  Tomoo Iijima ,  Hidetoshi Kusano

IPC分类号： H01L2144

CPC分类号： H05K3/4007 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/3025 ,  H05K3/205 ,  H05K3/243 ,  H01L2924/00014 ,  H01L2924/00

摘要： By adopting an electrolytic plating method in forming the bump, the drawbacks of the conventional electrolytic plating method should be avoided. For example, the necessity of adopting a lead wiring for each wiring or the like should be eliminated. On the surface of a metal base, a resist film (first resist film) having a negative pattern for forming a wiring film and a resist film (second resist film) having a negative pattern for forming the bump or the pad is formed. By using these films as masks, electrolytic plating of a bump material film is conducted to form the bump. Subsequently, after only the second film is removed. By using the first resist film as a mask, electrolytic plating is then conducted to form a wiring film.

摘要翻译： 通过在形成凸块时采用电解电镀方法，应避免常规电解电镀方法的缺点。 例如，应该消除对每个布线等采用引线的必要性。 在金属基体的表面上，形成具有用于形成布线膜的负图案的抗蚀剂膜（第一抗蚀剂膜）和具有用于形成凸块或焊盘的负图案的抗蚀剂膜（第二抗蚀剂膜）。 通过使用这些膜作为掩模，进行凸块材料膜的电解电镀以形成凸块。 随后，仅仅第二个膜被去除之后。 通过使用第一抗蚀剂膜作为掩模，然后进行电镀以形成布线膜。