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    Semiconductor device and semiconductor-device manufacturing method
    1.
    发明授权
    Semiconductor device and semiconductor-device manufacturing method 有权
    半导体器件和半导体器件制造方法

    公开(公告)号：US09287311B2

    公开(公告)日：2016-03-15

    申请号：US13587317

    申请日：2012-08-16

    申请人： Kan Shimizu ,  Keishi Inoue

    发明人： Kan Shimizu ,  Keishi Inoue

    IPC分类号： H01L27/14 ,  H01L27/146 ,  H01L23/48 ,  H01L21/44

    CPC分类号： H01L27/14636 ,  H01L21/76898 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2224/83 ,  H01L2924/00

    摘要： It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.

    摘要翻译： 可以降低连接通孔的元件与线的电阻变化，提高布线的可靠性。 产生贯通硅通孔穿过的孔，并对包括该线的布线层进行过蚀刻处理。 然后，通过将铜嵌入孔中，可以形成由铜制成的贯通硅通孔。 在通过作为连接区域的构件将通硅通孔连接到由铝制成的线之后，在热处理中合金化连接区域，以将通硅通孔电连接到线路。 因此，可以减小贯通硅通孔和线路之间的电阻的变化，并且还提高布线可靠性。 本技术可以应用于半导体器件和半导体器件的制造方法。

    Metal interconnect structure for integrated circuits and a design rule therefor
    4.
    发明授权
    Metal interconnect structure for integrated circuits and a design rule therefor 失效
    用于集成电路的金属互连结构及其设计规则

    公开(公告)号：US07251799B2

    公开(公告)日：2007-07-31

    申请号：US11215766

    申请日：2005-08-30

    申请人： Takeshi Nogami ,  Keishi Inoue

    发明人： Takeshi Nogami ,  Keishi Inoue

    IPC分类号： G06F17/50

    CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two. The layout of lines in the second level of metallization is arranged so that they partially overlap in the vertical direction one of the lines in the first level of metallization.

    摘要翻译： 提供了一种用于设计具有相对于预先存在的互连结构布局具有减小的横向尺寸的互连结构的集成电路的方法。 该方法首先通过将给定的金属化水平的每条导线的宽度减小到规定的宽度，从而将预定的互连结构布局中给定的金属化水平的横向尺寸减小所需的量。 导电线被电介质材料分开。 互连结构布局中给定的金属化水平被划分为至少第一级和第二级的金属化，通过在给定级别的第二级别的金属化交替的线中排列。 每条线的横向上的规定宽度在第一和第二金属化水平上增加至少两倍。 在第二级金属化中的线的布局被布置成使得它们在第一级金属化中的一条线上的垂直方向上部分重叠。

    Image display system using a common video memory for phased terminals
    5.
    发明授权
    Image display system using a common video memory for phased terminals 失效
    图像显示系统使用公共视频存储器进行相位终端

    公开(公告)号：US5602983A

    公开(公告)日：1997-02-11

    申请号：US49667

    申请日：1993-04-21

    申请人： Takashi Naba ,  Keishi Inoue

    发明人： Takashi Naba ,  Keishi Inoue

    IPC分类号： G06F3/147 ,  G11B27/10 ,  H04N1/21 ,  H04N1/32 ,  G06T1/00

    CPC分类号： H04N1/2179 ,  G06F3/147 ,  G11B27/105 ,  H04N1/32358 ,  H04N2201/0087 ,  H04N2201/0089 ,  H04N2201/3287

    摘要： An image display system for display image information obtained by accessing an image data base or the like which was stored in an electronic filing device. The system has: an electronic filing device to store a plurality of pieces of information; a plurality of terminal devices; a common image information memory such as a video RAM to store the image information read out of the electronic filing device on the basis of an instruction from at least one of the terminal devices; and a distributor to distribute and transfer the image information stored in the VRAM to any or all of the terminal devices in accordance with an image transfer instruction from such terminal device(s). A ferroelectric liquid crystal or other display panel which can hold the image information for a predetermined time may be used as a display. The display information can be individually effectively accessed from the electronic filing device by each terminal device while commonly using a single VRAM.

    摘要翻译： 一种图像显示系统，用于通过访问存储在电子文件装置中的图像数据库等获得显示图像信息。 该系统具有：存储多条信息的电子归档装置; 多个终端装置; 基于来自至少一个终端设备的指令，存储诸如视频RAM的公共图像信息存储器，用于存储从电子归档装置读出的图像信息; 以及根据来自这样的终端设备的图像传送指令，将存储在VRAM中的图像信息分发并传送到任何或所有终端设备的分发器。 可以将能够将图像信息保持预定时间的铁电液晶或其他显示面板用作显示器。 在通常使用单个VRAM时，可以通过每个终端设备从电子归档设备单独有效地访问显示信息。

    Semiconductor device and method of fabricating the same
    8.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07279791B2

    公开(公告)日：2007-10-09

    申请号：US10824229

    申请日：2004-04-14

    申请人： Keishi Inoue

    发明人： Keishi Inoue

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provides a semiconductor that enables to suppress deformation of the opening portions due to thermal expansion and contraction and to improve production yield and reliability wiring, and a method of fabricating the same. A first conductive layer and a second conductive layer are formed on a substrate. An insulation film is formed on upper surfaces of the first and second conductive layers and has a plurality of first opening portions to expose either the first or second conductive layer and a plurality of second opening portions to expose neither the first nor the second conductive layer. The second opening portions are formed between the first opening portions. A third conductive layer formed on an upper surface of the insulation film and has an electrical connection between the first and second conductive layers through the first opening portions.

    摘要翻译： 提供能够抑制由于热膨胀和收缩引起的开口部的变形并提高生产率和可靠性布线的半导体及其制造方法。 在基板上形成第一导电层和第二导电层。 绝缘膜形成在第一和第二导电层的上表面上，并且具有多个第一开口部分以暴露第一或第二导电层和多个第二开口部分，以使第一导电层和第二导电层都不露出。 第二开口部分形成在第一开口部分之间。 第三导电层，形成在绝缘膜的上表面上，并且通过第一开口部分在第一和第二导电层之间具有电连接。

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR-DEVICE MANUFACTURING METHOD
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR-DEVICE MANUFACTURING METHOD 有权
    半导体器件和半导体器件制造方法

    公开(公告)号：US20130082341A1

    公开(公告)日：2013-04-04

    申请号：US13587317

    申请日：2012-08-16

    申请人： Kan SHIMIZU ,  Keishi INOUE

    发明人： Kan SHIMIZU ,  Keishi INOUE

    IPC分类号： H01L23/48 ,  H01L31/18 ,  H01L27/14

    CPC分类号： H01L27/14636 ,  H01L21/76898 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2224/83 ,  H01L2924/00

    摘要： It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.

    摘要翻译： 可以减少将硅通孔连接到线路的部件的电阻变化，并提高接线可靠性。 产生贯通硅通孔穿过的孔，并对包括该线的布线层进行过蚀刻处理。 然后，通过将铜嵌入孔中，可以形成由铜制成的贯通硅通孔。 在通过作为连接区域的构件将通硅通孔连接到由铝制成的线之后，在热处理中合金化连接区域，以将通硅通孔电连接到线路。 因此，可以减小贯通硅通孔和线路之间的电阻的变化，并且还提高布线可靠性。 本技术可以应用于半导体器件和半导体器件的制造方法。

    Metal interconnect structure for integrated circuits and a design rule therefor
    10.
    发明申请
    Metal interconnect structure for integrated circuits and a design rule therefor 失效

    公开(公告)号：US20070045850A1

    公开(公告)日：2007-03-01

    申请号：US11215766

    申请日：2005-08-30

    申请人： Takeshi Nogami ,  Keishi Inoue

    发明人： Takeshi Nogami ,  Keishi Inoue

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for designing an integrated circuit having an interconnect structure with a reduced lateral dimension relative to a pre-existing interconnect structure layout. The method begins by reducing in scale by a desired amount the lateral dimension of a given level of metallization in the pre-existing interconnect structure layout by reducing the width of each conductive line in the given level of metallization to a prescribed width. The conductive lines are separated by dielectric material. The given level of metallization in the interconnect structure layout is divided into at least first and second levels of metallization by arranging in the second level of metallization alternating lines from the given level. The prescribed width in the lateral direction of each line is increased in the first and second levels of metallization by a factor of at least two. The layout of lines in the second level of metallization is arranged so that they partially overlap in the vertical direction one of the lines in the first level of metallization.