公开(公告)号：US20160276575A1

公开(公告)日：2016-09-22

申请号：US15170409

申请日：2016-06-01

申请人： Kyung-Tae NAM ,  Kil-Ho LEE

发明人： Kyung-Tae NAM ,  Kil-Ho LEE

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC分类号： H01L43/02 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： In a method of manufacturing an MRAM device, a lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern sequentially stacked on a substrate may be formed. A first insulating interlayer may be formed on the substrate to cover the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern. The first insulating interlayer may be etched to form a recess exposing a top surface of the free layer pattern. A second pinning layer pattern may be formed to fill at least a portion of the recess. A wiring may be formed on the second pinning layer pattern.

公开(公告)号：US20160020249A1

公开(公告)日：2016-01-21

申请号：US14804321

申请日：2015-07-20

申请人： Seung-Pil KO ,  Myoung-Su SON ,  Kil-Ho LEE

发明人： Seung-Pil KO ,  Myoung-Su SON ,  Kil-Ho LEE

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： An MRAM device comprises an insulating interlayer comprising a flat first upper surface on a first region and a second region of a substrate. A pattern structure comprising pillar-shaped magnetic tunnel junction (MTJ) structures and a filling layer pattern between the MTJ structures is formed on the insulating interlayer of the first region. The pattern structure comprises a flat second upper surface that is higher than the first upper surface. Bit lines are formed on the pattern structure that contact top surfaces of the MTJ structures. An etch-stop layer is formed on the pattern structure between the bit lines of the first region and the first upper surface of the first insulating interlayer of the second region. A first portion of an upper surface of the etch-stop layer on the first region is higher than a second portion of the upper surface of the etch-stop layer on the second region.

摘要翻译： MRAM器件包括绝缘中间层，其包括在第一区域上的平坦的第一上表面和衬底的第二区域。 在第一区域的绝缘中间层上形成包括柱形磁隧道结（MTJ）结构和MTJ结构之间的填充层图案的图案结构。 图案结构包括比第一上表面高的扁平的第二上表面。 位线形成在与MTJ结构的顶表面接触的图案结构上。 在第一区域的位线和第二区域的第一绝缘中间层的第一上表面之间的图案结构上形成蚀刻停止层。 第一区域上的蚀刻停止层的上表面的第一部分高于第二区域上的蚀刻停止层的上表面的第二部分。

公开(公告)号：US20140264516A1

公开(公告)日：2014-09-18

申请号：US14210329

申请日：2014-03-13

申请人： Bum-Seok SEO ,  Ki-Joon KIM ,  Kil-Ho LEE

发明人： Bum-Seok SEO ,  Ki-Joon KIM ,  Kil-Ho LEE

IPC分类号： H01L43/02 ,  H01L43/12

CPC分类号： H01L27/228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

摘要翻译： 在基板上形成绝缘层。 在绝缘层上形成第一掩模。 第一掩模包括沿第二方向布置的多个线图案。 多个线图案沿着基本上垂直于第二方向的第一方向延伸。 在绝缘层和第一掩模上形成第二掩模。 第二掩模包括部分地暴露多个线图案的开口。 开口在第一方向的第一端部和第一方向的第三方向的第二方向的第一方向的一侧具有不均匀的边界。 使用第一掩模和第二掩模作为蚀刻掩模来部分去除绝缘层，从而形成多个第一沟槽和第二沟槽。 多个第一沟槽和第二沟槽以交错图案布置。

公开(公告)号：US06329237B1

公开(公告)日：2001-12-11

申请号：US09466896

申请日：1999-12-20

申请人： Kyong Min Kim ,  Chan Lim ,  Kil Ho Lee ,  Ki Seon Park

发明人： Kyong Min Kim ,  Chan Lim ,  Kil Ho Lee ,  Ki Seon Park

IPC分类号： H01L218242

CPC分类号： H01L21/31691 ,  C23C16/405 ,  C23C16/409 ,  C23C16/56 ,  H01L28/55

摘要： There is disclosed a method of making a high dielectric capacitor of a semiconductor device using Ta2O5, BST((Ba1−xSrx)TiO3) etc. of a high dielectric characteristic as a capacitor dielectric film in a very high integrated memory device. The present invention has its object to provide a method of manufacturing a high dielectric capacitor of a semiconductor device, which can effectively remove carbon contained within the thin film after deposition of the BST film and defects of oxygen depletion caused upon deposition of the thin film and which can also remove carbon contained within the thin film after deposition of the tantalum oxide film and defects of oxygen depletion caused upon deposition of the thin film, without further difficult processes or without any deterioration of the electrical characteristic of the capacitor. It employs the technology which is able to effectively removing defects of carbon and oxygen depletion within the thin film, by forming a plasma O3 gas having a good reactivity and by processing the plasma for the BST thin film and tantalum oxide film. Thus, it can extend the lifetime of the activated oxygen of oxygen, which had been a problem in processing a conventional UV-O3, by means of plasma process using O3 gas. Therefore, it can effectively remove defects of carbon and oxygen within the BST thin film and tantalum oxide film without complicating the process or deteriorating the electrical characteristic of the capacitor. The present invention also proposes a detailed process condition, which can optimize the plasma process using O3 gas.

摘要翻译： 公开了在非常高的集成存储器件中使用具有高介电特性的Ta2O5，BST（（Ba1-xSrx）TiO3）等作为电容器电介质膜的半导体器件的高介电电容器的方法。 本发明的目的是提供一种制造半导体器件的高介电电容器的方法，其可以有效地去除沉积BST膜之后的薄膜中包含的碳和沉积薄膜时引起的氧耗损缺陷， 其也可以在沉积氧化钽膜之后，除去薄膜中所含的碳和沉积薄膜所引起的氧耗尽的缺陷，而不需要进一步的困难处理或不会使电容器的电特性恶化。 通过形成具有良好反应性的等离子体O 3气体和通过处理BST薄膜和氧化钽膜的等离子体，采用能够有效地去除薄膜内的碳和氧缺乏的缺陷的技术。 因此，通过使用O 3气体的等离子体处理，可以延长氧气的活化氧的寿命，这在处理常规的UV-O 3中是一个问题。 因此，可以有效地去除BST薄膜和氧化钽膜内的碳和氧的缺陷，而不会使工艺复杂化或劣化电容器的电特性。 本发明还提出了一种详细的工艺条件，其可以优化使用O 3气体的等离子体工艺。

公开(公告)号：US5872047A

公开(公告)日：1999-02-16

申请号：US871850

申请日：1997-06-09

申请人： Kil Ho Lee ,  Sang Ho Yu

发明人： Kil Ho Lee ,  Sang Ho Yu

IPC分类号： H01L29/78 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/425

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/823418

摘要： A method for forming a shallow junction of a semiconductor device, characterized by a rapid thermal process executed to considerably decrease the density of the point defects which may be caused by ion implantation. With it, a junction which is much shallower, with lower sheet resistance and less junction leakage current can be obtained even under conventional ion implantation and tube treatment conditions. This contributes to an improvement in the production yield of a semiconductor device. By virtue of the elimination of the point defects, the limits in selecting the tube thermal treatment temperature and time for planarizing the subsequent interlayer insulating film can be relieved, so that process allowance can be secured, thereby improving the reliability of the semiconductor device and allowing the high integration of the semiconductor device.

摘要翻译： 一种用于形成半导体器件的浅结的方法，其特征在于执行快速热处理以显着降低由离子注入引起的点缺陷的密度。 因此，即使在常规的离子注入和管处理条件下，也可以获得更浅的结，具有较低的薄层电阻和较少的结漏电流。 这有助于提高半导体器件的产量。 由于消除点缺陷，可以减轻选择用于平坦化后续层间绝缘膜的管热处理温度和时间的限制，从而可以确保工艺余量，从而提高半导体器件的可靠性并允许 半导体器件的高集成度。

公开(公告)号：US5683920A

公开(公告)日：1997-11-04

申请号：US768940

申请日：1996-12-18

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L27/092 ,  H01L21/335 ,  H01L21/8238

CPC分类号： H01L21/823814

摘要： A method for fabricating a semiconductor device which is capable of forming an ultra-shallow junction causing no defect in source/drain regions. The method includes the steps of providing a semiconductor substrate formed with n and p type wells and element-isolating films, forming gate oxide films on the n and p type wells, respectively, forming a polysilicon film over the entire exposed upper surface of the resulting structure, implanting first impurity ions having an n type conductivity in a portion of the polysilicon film disposed over the p type well, implanting first impurity ions having a p type conductivity in a portion of the polysilicon film disposed over the n type well, implanting second impurity ions having the p type conductivity in portions of the polysilicon film except for portions which will be used as gate electrodes, annealing the resulting structure in such a manner that the first impurity ions having the p type conductivity are diffused into the n type well, thereby forming p.sup.+ source/drain, selectively removing the polysilicon film, thereby forming n and p type gate electrodes, and implanting second impurity ions having the n type conductivity in an exposed surface portion of the p type well, thereby forming n.sup.+ source/drain.

摘要翻译： 一种制造半导体器件的方法，该半导体器件能够形成在源极/漏极区域中不产生缺陷的超浅结。 该方法包括以下步骤：提供形成有n型和p型阱和元件隔离膜的半导体衬底，分别在n型和p型阱上形成栅极氧化膜，在所得到的整个暴露的上表面上形成多晶硅膜 结构，在位于p型阱上的多晶硅膜的一部分中注入具有n型导电性的第一杂质离子，在第n型阱上设置多晶硅膜的部分中注入具有p型导电性的第一杂质离子，注入第二杂质 除了将用作栅电极的部分之外，在多晶硅膜的部分中具有p型导电性的离子，以使得具有p型导电性的第一杂质离子扩散到n型阱中的方式退火所得到的结构，从而 形成p +源极/漏极，选择性地去除多晶硅膜，由此形成n型和p型栅电极，以及植入第二阻挡层 y型离子在p型阱的露出表面部分具有n型导电性，从而形成n +源极/漏极。

公开(公告)号：US5677213A

公开(公告)日：1997-10-14

申请号：US604909

申请日：1996-02-22

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L21/285 ,  H01L21/225 ,  H01L21/336 ,  H01L21/266

CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L29/41783 ,  H01L29/6659

摘要： In accordance with an aspect of the present invention, there is provided a method for forming a junction of a low sheet resistance on a silicon substrate, comprising the steps of forming an amorphous silicon layer on said silicon substrate; implanting impurity ions into said amorphous silicon layer; implanting transition metal ions into said amorphous silicon layer; and thermally treating said amorphous silicon layer and silicon substrate such that said transition metal ions diffuse to the surface of said silicon substrate and said impurity ions diffuse into said silicon substrate.

摘要翻译： 根据本发明的一个方面，提供了一种在硅衬底上形成低电阻的接合的方法，包括以下步骤：在所述硅衬底上形成非晶硅层; 将杂质离子注入所述非晶硅层; 将过渡金属离子注入所述非晶硅层; 以及热处理所述非晶硅层和硅衬底，使得所述过渡金属离子扩散到所述硅衬底的表面，并且所述杂质离子扩散到所述硅衬底中。

公开(公告)号：US20170069684A1

公开(公告)日：2017-03-09

申请号：US15157403

申请日：2016-05-17

申请人： Ki-Seok SUH ,  Jae-Chul SHIM ,  Kil-Ho LEE ,  Yong-Seok CHUNG ,  Gwan-Hyeob KOH ,  Yoon-Jong SONG

发明人： Ki-Seok SUH ,  Jae-Chul SHIM ,  Kil-Ho LEE ,  Yong-Seok CHUNG ,  Gwan-Hyeob KOH ,  Yoon-Jong SONG

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

CPC分类号： H01L27/222 ,  H01L43/12

摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

摘要翻译： 制造MRAM器件的方法包括在衬底上依次形成第一绝缘层和蚀刻停止层。 通过蚀刻停止层和第一绝缘中间层形成下电极。 在下电极和蚀刻停止层上依次形成MTJ结构层和上电极。 通过使用上电极作为蚀刻掩模的物理蚀刻工艺对MTJ结构层进行构图，以形成至少部分地接触下电极的MTJ结构。 第一绝缘中间层由蚀刻停止层保护，因此不被物理蚀刻工艺蚀刻。

公开(公告)号：US09118002B2

公开(公告)日：2015-08-25

申请号：US14210329

申请日：2014-03-13

申请人： Bum-Seok Seo ,  Ki-Joon Kim ,  Kil-Ho Lee

发明人： Bum-Seok Seo ,  Ki-Joon Kim ,  Kil-Ho Lee

IPC分类号： H01L43/02 ,  H01L43/12 ,  H01L21/311 ,  H01L29/82 ,  H01L21/033 ,  H01L21/768

CPC分类号： H01L27/228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

摘要翻译： 在基板上形成绝缘层。 在绝缘层上形成第一掩模。 第一掩模包括沿第二方向布置的多个线图案。 多个线图案沿着基本上垂直于第二方向的第一方向延伸。 在绝缘层和第一掩模上形成第二掩模。 第二掩模包括部分地暴露多个线图案的开口。 开口在第一方向的第一端部和第一方向的第三方向的第二方向的第一方向的一侧具有不均匀的边界。 使用第一掩模和第二掩模作为蚀刻掩模来部分去除绝缘层，从而形成多个第一沟槽和第二沟槽。 多个第一沟槽和第二沟槽以交错图案布置。

公开(公告)号：US07655099B2

公开(公告)日：2010-02-02

申请号：US12117274

申请日：2008-05-08

申请人： Kil-Ho Lee ,  Chan Lim

发明人： Kil-Ho Lee ,  Chan Lim

IPC分类号： H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  Y10S257/914 ,  H01L2924/00

摘要： A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.

摘要翻译： 提供了高k电介质膜，形成高k电介质膜的方法以及形成相关半导体器件的方法。 高k电介质膜包括具有第一氮含量和第一硅含量的金属 - 氮氧化硅的底层和具有第二氮含量和第二硅含量的金属 - 氮氧化硅的顶层。 第二氮含量高于第一氮含量，第二硅含量高于第一硅含量。