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    III-V power field effect transistors
    1.
    发明授权
    III-V power field effect transistors 有权
    III-V功率场效应晶体管

    公开(公告)号：US07180103B2

    公开(公告)日：2007-02-20

    申请号：US10948897

    申请日：2004-09-24

    申请人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

    发明人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

    IPC分类号： H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC分类号： H01L29/4983 ,  H01L29/812

    摘要： A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

    摘要翻译： 公开了一种配置用于大功率应用的场效应晶体管及其制造方法。 场效应晶体管由III-V材料形成，并且被配置为具有对大功率应用有利的击穿电压。 通过确定该工作电压的工作电压和期望的击穿电压来配置场效应晶体管。 然后识别与工作电压和期望的击穿电压相关联的峰值电场。 然后将该器件配置为在该工作电压下呈现鉴定的峰值电场。 通过选择控制器件漂移区域中的电位的器件特征来实现该器件的配置。 这些特征包括使用重叠的栅极或场板结合覆盖器件沟道的势垒层，或形成在器件沟道下形成的单晶III-V材料区域中的p型阱。 重叠的栅极/场板或p型阱延伸到器件的漂移区域中，以提供对漂移区域中的电势的期望控制的方式控制器件的电位。

    III-V power field effect transistors
    2.
    发明授权
    III-V power field effect transistors 失效
    III-V功率场效应晶体管

    公开(公告)号：US07537984B2

    公开(公告)日：2009-05-26

    申请号：US11641507

    申请日：2006-12-19

    申请人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

    发明人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

    IPC分类号： H01L21/338

    CPC分类号： H01L29/4983 ,  H01L29/812

    摘要： A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

    摘要翻译： 公开了一种配置用于大功率应用的场效应晶体管及其制造方法。 场效应晶体管由III-V材料形成，并且被配置为具有对大功率应用有利的击穿电压。 通过确定该工作电压的工作电压和期望的击穿电压来配置场效应晶体管。 然后识别与工作电压和期望的击穿电压相关联的峰值电场。 然后将该器件配置为在该工作电压下呈现鉴定的峰值电场。 通过选择控制器件漂移区域中的电位的器件特征来实现该器件的配置。 这些特征包括使用重叠的栅极或场板结合覆盖器件沟道的势垒层，或形成在器件沟道下形成的单晶III-V材料区域中的p型阱。 重叠的栅极/场板或p型阱延伸到器件的漂移区域中，以提供对漂移区域中的电势的期望控制的方式控制器件的电位。

    Process for fabricating bipolar and BiCMOS devices
    3.
    发明授权
    Process for fabricating bipolar and BiCMOS devices 失效
    制造双极和BiCMOS器件的工艺

    公开(公告)号：US06121101A

    公开(公告)日：2000-09-19

    申请号：US42388

    申请日：1998-03-12

    申请人： Clifford Alan King ,  Kwok K. Ng

    发明人： Clifford Alan King ,  Kwok K. Ng

    IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

    CPC分类号： H01L21/8249

    摘要： A process for device fabrication in which amorphous silicon is deposited into a narrow gap is disclosed. The gap is an opening between two layers of material. The gap results when a window is formed in one of the two layers and a portion of a third layer at the base of the window is removed. In the formation of a bipolar device, a layer of oxide is formed on a silicon substrate and a layer of silicon is formed on the oxide layer which serves as the extrinsic base for the device. In the bipolar device, a window is formed in the polysilicon and the oxide layer at the base of the window is then removed. In the bipolar device, the silicon substrate underlies the gap and the extrinsic base silicon overlies the gap. When the oxide is removed from the base of the window, a portion of the oxide layer underlying the extrinsic base silicon is removed as well, thereby forming a gap between the extrinsic base silicon and the underlying silicon substrate. In the process of the present invention, the resulting gap has a proximate end which is the opening of the gap into a window and a distal end which is the interface between the gap and the remaining oxide. The width of the gap is less than about 20 nm. The gap is then subjected to conditions that cause the gap to have a first height at its proximate end which is greater than its height at its distal end. The tapered gap is then filled with polysilicon. Because of its tapered configuration, the polysilicon uniformly fills the gap, without significant voids therein.

    摘要翻译： 公开了一种其中非晶硅沉积到窄间隙中的器件制造工艺。 间隙是两层材料之间的开口。 当窗口形成在两个层中的一个层中并且在窗口的基部处的第三层的一部分被去除时，产生间隙。 在双极器件的形成中，在硅衬底上形成氧化物层，并且在作为器件的外在基极的氧化物层上形成硅层。 在双极器件中，在多晶硅中形成窗口，然后去除窗口底部的氧化物层。 在双极器件中，硅衬底位于间隙之下，而外部基极硅覆盖在间隙上。 当从窗口的底部去除氧化物时，除去外部基底硅下面的一部分氧化物层，从而在外部基极硅和下面的硅衬底之间形成间隙。 在本发明的方法中，所得到的间隙具有近端，该近端是间隙进入窗口的开口，而远端是间隙和剩余氧化物之间的界面。 间隙的宽度小于约20nm。 然后使间隙受到使其间隙在其近端具有大于其远端高度的第一高度的条件。 然后用多晶硅填充锥形间隙。 由于其锥形构造，多晶硅均匀地填充间隙，其中没有显着的空隙。

    Semiconductor-on-insulator (SOI) devices and SOI IC fabrication method
    4.
    发明授权
    Semiconductor-on-insulator (SOI) devices and SOI IC fabrication method 失效
    绝缘体上半导体（SOI）器件和SOI IC制造方法

    公开(公告)号：US4763183A

    公开(公告)日：1988-08-09

    申请号：US921899

    申请日：1986-10-24

    申请人： Kwok K. Ng ,  Simon M. Sze

    发明人： Kwok K. Ng ,  Simon M. Sze

    IPC分类号： H01L21/74 ,  H01L21/86 ,  H01L23/482 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L29/48 ,  H01L29/80

    CPC分类号： H01L29/78648 ,  H01L21/743 ,  H01L21/86 ,  H01L23/4825 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78612 ,  H01L2924/0002

    摘要： A new SOI device which permits both the kink effect to be avoided and threshold voltage to be regulated, as well as a new method for fabricating SOI ICs, is disclosed. The new device included an electrically conductive pathway extending from the active volume and terminating in a non-active region of the substrate of the device. A back-gate bias is communicated to, and kink-inducing charges are conducted away from, the active volume through the conductive pathway. The new fabrication methd permits SOI ICs to be fabricated using available circuit designs and pattern delineating apparatus, e.g., IC mask sets. This method involves the formation of a precursor substrate surface which includes islands of insulating material, each of which is encircled by a crystallization seeding area of substantially single crystal semiconductor material. The boundaries of the islands are defined with a first pattern delineating device, e.g., a mask, which, in terms of the pattern it produces, is substantially identical to a second pattern delineating device. The latter device is a component of pattern delineating apparatus used in forming an IC, e.g., an IC mask set, the component being used to delineate the device regions of the IC. A layer of non-single crystal semiconductor material is formed on the precursor substrate surface, and crystallized with little or no displacement of the islands. The pattern delineating apparatus is then used to form an IC in the crystallized material.

    摘要翻译： 公开了允许避免扭结效应和阈值电压被调节的新的SOI器件，以及制造SOI IC的新方法。 新器件包括从有源体积延伸并终止在器件的衬底的非有源区域中的导电通路。 通过导通路径将反向栅极偏压传送到负极，并且将导通电荷从有源体积传导出去。 新的制造方法允许使用可用的电路设计和图案描绘装置（例如，IC掩模组）制造SOI IC。 该方法包括形成包括绝缘材料岛的前体衬底表面，每个绝缘材料岛由基本单晶半导体材料的结晶晶种区域包围。 岛的边界由第一图案描绘装置（例如掩模）来限定，根据其形成的图案，其基本上与第二图案描绘装置相同。 后一种装置是用于形成IC的图案描绘装置的部件，例如IC掩模组，该部件用于描绘IC的装置区域。 在前体衬底表面上形成一层非单晶半导体材料，并且很少或没有岛的位移结晶。 然后使用图案描绘装置在结晶材料中形成IC。

    Test circuit for measuring specific contact resistivity of self-aligned contacts in integrated circuits
    7.
    发明授权
    Test circuit for measuring specific contact resistivity of self-aligned contacts in integrated circuits 失效
    用于测量集成电路中自对准触点的特定接触电阻的测试电路

    公开(公告)号：US4896108A

    公开(公告)日：1990-01-23

    申请号：US224512

    申请日：1988-07-25

    申请人： William T. Lynch ,  Kwok K. Ng

    发明人： William T. Lynch ,  Kwok K. Ng

    IPC分类号： G01R31/26 ,  G01R27/14 ,  G01R31/27 ,  H01L21/28 ,  H01L21/66 ,  H01L23/544

    CPC分类号： H01L22/34 ,  G01R27/14 ,  G01R31/275 ,  H01L2924/3011

    摘要： A test circuit is described for measuring the specific contact resistivity r.sub.c of self-aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance r.sub.s of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region, a self-aligned common controlled electrode contacting a diffused region underneath it, and a common control electrode. During test operation, both est transistors are kept ON by means of an applied above-threshold control voltage, while a current source forces current through one of the transistors. The resulting voltage, developed across the common controlled electrode and the controlled electrode of the other transistor is a measure of the specific contact resistivity thereat.

    Packaging microminiature devices
    8.
    依法登记的发明
    Packaging microminiature devices 失效
    包装微型设备

    公开(公告)号：USH208H

    公开(公告)日：1987-02-03

    申请号：US581336

    申请日：1984-02-17

    申请人： Kwok K. Ng ,  Simon M. Sze

    发明人： Kwok K. Ng ,  Simon M. Sze

    IPC分类号： H01L23/14 ,  H01L23/522 ,  H01L23/538 ,  H01L23/64

    CPC分类号： H01L23/5222 ,  H01L23/147 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00

    摘要： One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.