公开(公告)号：US4613891A

公开(公告)日：1986-09-23

申请号：US581259

申请日：1984-02-17

申请人： Kwok K. Ng ,  Simon M. Sze

发明人： Kwok K. Ng ,  Simon M. Sze

IPC分类号： H01L23/12 ,  H01L23/14 ,  H01L23/522 ,  H01L23/538 ,  H01L23/64 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52

CPC分类号： H01L24/82 ,  H01L23/147 ,  H01L23/5222 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/642 ,  H01L24/18 ,  H01L2224/18 ,  H01L2224/92144 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107

摘要： One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

摘要翻译： 一个或多个硅集成电路芯片从主动侧向上连接到硅晶片的底侧。 在每个连接的芯片的活动侧的一部分对准的晶片中蚀刻倾斜的壁通孔。 然后在晶片的顶侧和倾斜壁上形成光刻定义的导电图案，以将每个芯片上的导电焊盘连接到其它芯片上的导电焊盘和/或沿着晶片周边设置的导电端子。 所得到的封装芯片组件具有有利的性能和成本特征。

公开(公告)号：US4763183A

公开(公告)日：1988-08-09

申请号：US921899

申请日：1986-10-24

申请人： Kwok K. Ng ,  Simon M. Sze

发明人： Kwok K. Ng ,  Simon M. Sze

IPC分类号： H01L21/74 ,  H01L21/86 ,  H01L23/482 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L29/48 ,  H01L29/80

CPC分类号： H01L29/78648 ,  H01L21/743 ,  H01L21/86 ,  H01L23/4825 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78612 ,  H01L2924/0002

摘要： A new SOI device which permits both the kink effect to be avoided and threshold voltage to be regulated, as well as a new method for fabricating SOI ICs, is disclosed. The new device included an electrically conductive pathway extending from the active volume and terminating in a non-active region of the substrate of the device. A back-gate bias is communicated to, and kink-inducing charges are conducted away from, the active volume through the conductive pathway. The new fabrication methd permits SOI ICs to be fabricated using available circuit designs and pattern delineating apparatus, e.g., IC mask sets. This method involves the formation of a precursor substrate surface which includes islands of insulating material, each of which is encircled by a crystallization seeding area of substantially single crystal semiconductor material. The boundaries of the islands are defined with a first pattern delineating device, e.g., a mask, which, in terms of the pattern it produces, is substantially identical to a second pattern delineating device. The latter device is a component of pattern delineating apparatus used in forming an IC, e.g., an IC mask set, the component being used to delineate the device regions of the IC. A layer of non-single crystal semiconductor material is formed on the precursor substrate surface, and crystallized with little or no displacement of the islands. The pattern delineating apparatus is then used to form an IC in the crystallized material.

摘要翻译： 公开了允许避免扭结效应和阈值电压被调节的新的SOI器件，以及制造SOI IC的新方法。 新器件包括从有源体积延伸并终止在器件的衬底的非有源区域中的导电通路。 通过导通路径将反向栅极偏压传送到负极，并且将导通电荷从有源体积传导出去。 新的制造方法允许使用可用的电路设计和图案描绘装置（例如，IC掩模组）制造SOI IC。 该方法包括形成包括绝缘材料岛的前体衬底表面，每个绝缘材料岛由基本单晶半导体材料的结晶晶种区域包围。 岛的边界由第一图案描绘装置（例如掩模）来限定，根据其形成的图案，其基本上与第二图案描绘装置相同。 后一种装置是用于形成IC的图案描绘装置的部件，例如IC掩模组，该部件用于描绘IC的装置区域。 在前体衬底表面上形成一层非单晶半导体材料，并且很少或没有岛的位移结晶。 然后使用图案描绘装置在结晶材料中形成IC。

公开(公告)号：USH208H

公开(公告)日：1987-02-03

申请号：US581336

申请日：1984-02-17

申请人： Kwok K. Ng ,  Simon M. Sze

发明人： Kwok K. Ng ,  Simon M. Sze

IPC分类号： H01L23/14 ,  H01L23/522 ,  H01L23/538 ,  H01L23/64

CPC分类号： H01L23/5222 ,  H01L23/147 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00

摘要： One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

公开(公告)号：US4343082A

公开(公告)日：1982-08-10

申请号：US141120

申请日：1980-04-17

申请人： Martin P. Lepselter ,  Simon M. Sze

发明人： Martin P. Lepselter ,  Simon M. Sze

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/338 ,  H01L21/768 ,  H01L29/812 ,  C23F1/02 ,  B01J17/00 ,  B05D5/12 ,  C23C11/08

CPC分类号： H01L29/41783 ,  H01L21/28 ,  H01L21/28518

摘要： In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10.1, 10.2) as well as the silicon gate electrode (13).

摘要翻译： 在金属氧化物半导体场效应晶体管（MOSFET）或金属栅极场效应晶体管（MESFET）的制造中，其特征在于多晶硅栅极（13）和约微米或更小的短沟道，步骤 涉及通过用诸如铂的过渡金属的轰击同时形成源极，漏极和栅极电极接触，其在源极和漏极区域（10.1,10.2）上形成金属硅化物层（19,21,18） ）以及硅栅电极（13）。

公开(公告)号：US08071458B1

公开(公告)日：2011-12-06

申请号：US12953601

申请日：2010-11-24

申请人： Po-Tsun Liu ,  Chen-Shuo Huang ,  Yi-Ling Huang ,  Szu-Lin Cheng ,  Simon M. Sze ,  Yoshio Nishi

发明人： Po-Tsun Liu ,  Chen-Shuo Huang ,  Yi-Ling Huang ,  Szu-Lin Cheng ,  Simon M. Sze ,  Yoshio Nishi

IPC分类号： H01L21/02

CPC分类号： H01L21/02164 ,  H01L21/02343 ,  H01L21/28255

摘要： The invention discloses a method for forming an interfacial passivation layer on the Ge semiconductor. The supercritical CO2 fluids is used to form an interfacial passivation layer between Ge channel and gate insulator layer, and improve the dielectric characteristics of gate insulator after high-temperature thermal annealing process.

摘要翻译： 本发明公开了一种在Ge半导体上形成界面钝化层的方法。 超临界CO2流体用于在Ge通道和栅极绝缘体层之间形成界面钝化层，提高高温热退火工艺后栅极绝缘体的介电特性。

公开(公告)号：US06110809A

公开(公告)日：2000-08-29

申请号：US102675

申请日：1998-06-23

申请人： Simon M. Sze ,  Shih-Hsiung Chan ,  Jian-Shihn Tsang ,  Jan-Dar Guo ,  Wei-Chi Lai

发明人： Simon M. Sze ,  Shih-Hsiung Chan ,  Jian-Shihn Tsang ,  Jan-Dar Guo ,  Wei-Chi Lai

IPC分类号： C30B25/02 ,  H01L21/205 ,  H01L21/20

CPC分类号： C30B25/02 ,  C30B29/40 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/0254 ,  H01L21/0262

摘要： A new method for manufacturing a Group III metal nitride epitaxial wafer comprises providing a first nitrogen-contained gas source, providing a second Group III metal trichloride--containing gas source, and causing said first gas to react with second gas in a heating region, thereby forming a Group III metal nitride epitaxial layer on a substrate. The formed epitaxial wafer can serve as a substrate of a laser diode.

摘要翻译： 一种用于制造III族金属氮化物外延晶片的新方法包括提供第一含氮气体源，提供第二III族金属三氯化物气体源，并使所述第一气体与加热区域中的第二气体反应，由此 在基板上形成III族金属氮化物外延层。 所形成的外延晶片可以用作激光二极管的基板。

公开(公告)号：US4259680A

公开(公告)日：1981-03-31

申请号：US141119

申请日：1980-04-17

申请人： Martin P. Lepselter ,  Simon M. Sze

发明人： Martin P. Lepselter ,  Simon M. Sze

IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/331 ,  H01L23/532 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/735 ,  H01L29/04 ,  H01L29/72

CPC分类号： H01L29/1008 ,  H01L21/2257 ,  H01L23/53271 ,  H01L29/42304 ,  H01L29/735 ,  H01L2924/0002

摘要： A bipolar transistor NPN structure (20) is constructed at a major surface of a silicon body with a P-type polycrystalline silicon electrode (13) contacting a P-type base zone (13.6). Excess acceptor impurities from the polycrystalline silicon electrode (13) are diffused into the base zone (13.6) in order to tailor its conductivity profile.

摘要翻译： 双极晶体管NPN结构（20）由与P型基极区（13.6）接触的P型多晶硅电极（13）构成在硅体的主表面。 来自多晶硅电极（13）的过多的受主杂质扩散到基区（13.6）中，以便调整其导电性。

公开(公告)号：US06448584B1

公开(公告)日：2002-09-10

申请号：US09482602

申请日：2000-01-14

申请人： Shih-Hsiung Chan ,  Jian-Shihn Tsang ,  Jan-Dar Guo ,  Simon M. Sze

发明人： Shih-Hsiung Chan ,  Jian-Shihn Tsang ,  Jan-Dar Guo ,  Simon M. Sze

IPC分类号： H01L2912

CPC分类号： H01L33/02 ,  H01L33/14 ,  H01L33/30

摘要： The present invention relates to a light emitting diode with high luminance and method for making the same, and more particularly to a light emitting diode having a transparent window layer which is formed by a semiconductor film of nitrogen-containing compounds. The present invention is mainly directed to growing a window layer of a light emitting diode with a nitrogen-containing compound on the double heterostructure of InGaAlP. Since the energy gap of the nitrogen-containing compound is greater than that of the light emitted from the active layer and is smaller than that of GaP, it is easily to be doped and to form metallic ohmic electrode. Therefore, it is suitable to form a window layer, thereby increasing the light emitting efficiency of a light emitting diode. In addition, the nitrogen-containing compounds can be formed by the current MBE or OMVPE techniques. Therefore, the light emitting diode can be mass-produced and does have industrial applicability.

摘要翻译： 本发明涉及一种具有高亮度的发光二极管及其制造方法，更具体地说，涉及具有由含氮化合物的半导体膜形成的透明窗口层的发光二极管。 本发明主要涉及在InGaAlP的双异质结构上生长具有含氮化合物的发光二极管的窗口层。 由于含氮化合物的能隙大于从有源层发射的光的能隙，并且小于GaP的能隙，因此容易被掺杂并形成金属欧姆电极。 因此，适合形成窗口层，由此提高发光二极管的发光效率。 此外，含氮化合物可以通过目前的MBE或OMVPE技术形成。 因此，发光二极管可以批量生产并且具有工业适用性。

公开(公告)号：US4737233A

公开(公告)日：1988-04-12

申请号：US901975

申请日：1986-09-02

申请人： Avid Kamgar ,  Ernest Labate ,  Joseph R. Ligenza ,  Simon M. Sze

发明人： Avid Kamgar ,  Ernest Labate ,  Joseph R. Ligenza ,  Simon M. Sze

IPC分类号： C30B13/22 ,  C30B13/24

CPC分类号： C30B13/24 ,  C30B13/22

摘要： Semiconductor crystal films on a dielectric substrate are advantageously made by a zone melting method. Single-crystal structure is initiated at a seed surface, and made to extend across a dielectric surface by melting and resolidifying.Melting is effected upon irradiation with optical radiation which is focused onto an elongated zone; the zone is moved so as to locally melt successive portions of a layer of precursor material which may be amorphous or polycrystalline. The use of incoherent radiation is convenient, and focusing is typically by using a reflector.The process is conveniently effected under a controlled atmosphere and the layer being crystallized may be encapsulated so that no free semiconductor surface is exposed to an atmosphere.

摘要翻译： 电介质基板上的半导体晶体膜有利地通过区域熔融法制成。 单晶结构在种子表面开始，并通过熔化和重新固化而延伸穿过电介质表面。 熔融是在被聚焦在细长区上的光辐射照射时进行的; 移动该区域以便局部熔化可能是无定形或多晶的前体材料层的连续部分。 使用非相干辐射是方便的，并且聚焦通常是通过使用反射器。 该方法方便地在可控气氛下进行，并且被结晶的层可以被包封，使得没有游离半导体表面暴露于大气中。

公开(公告)号：USRE32613E

公开(公告)日：1988-02-23

申请号：US756924

申请日：1985-07-19

申请人： Martin P. Lepselter ,  Simon M. Sze

发明人： Martin P. Lepselter ,  Simon M. Sze

IPC分类号： H01L21/033 ,  H01L21/285 ,  H01L21/321 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/033 ,  H01L21/28518 ,  H01L21/321 ,  H01L29/41783

摘要： In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10.1, 10.2) as well as the silicon gate electrode (13).