公开(公告)号：US08572524B2

公开(公告)日：2013-10-29

申请号：US11943591

申请日：2007-11-21

申请人： Wenzhan Zhou ,  Liang Choo Hsia ,  Meisheng Zhou ,  Zheng Zou

发明人： Wenzhan Zhou ,  Liang Choo Hsia ,  Meisheng Zhou ,  Zheng Zou

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： An optical proximity correction (OPC) model incorporates inline process variation data. OPC is performed by adjusting an input mask pattern with a mask bias derived from the OPC model to correct errors in the input mask pattern.

摘要翻译： 光学邻近校正（OPC）模型包含在线过程变化数据。 通过使用从OPC模型导出的掩模偏差调整输入掩模图案来校正输入掩模图案中的错误来执行OPC。

公开(公告)号：US08354347B2

公开(公告)日：2013-01-15

申请号：US11953881

申请日：2007-12-11

申请人： Jianhui Ye ,  Huang Liu ,  Alex K H See ,  Wei Lu ,  Chun Hui Low ,  Chim Seng Seet ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jianhui Ye ,  Huang Liu ,  Alex K H See ,  Wei Lu ,  Chun Hui Low ,  Chim Seng Seet ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/461

CPC分类号： H01L21/76832 ,  H01L21/76895 ,  H01L21/76897

摘要： A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

公开(公告)号：US08293545B2

公开(公告)日：2012-10-23

申请号：US11927658

申请日：2007-10-29

申请人： Hai Cong ,  Yan Shan Li ,  Chun Hui Low ,  Yelehanka Ramachandramurthy Pradeep ,  Liang Choo Hsia

发明人： Hai Cong ,  Yan Shan Li ,  Chun Hui Low ,  Yelehanka Ramachandramurthy Pradeep ,  Liang Choo Hsia

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L23/58 ,  H01L29/10

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.

摘要翻译： 包括测试沟槽的测试结构用于定义集成电路的通孔级中的沟槽的临界尺寸，以产生基本上相同的深度。 沟槽形成在IC的外围，用作保护环。

公开(公告)号：US08293544B2

公开(公告)日：2012-10-23

申请号：US12220792

申请日：2008-07-28

申请人： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/00

CPC分类号： H01L27/088 ,  H01L27/0211

摘要： A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

摘要翻译： 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。

公开(公告)号：US08289508B2

公开(公告)日：2012-10-16

申请号：US12621510

申请日：2009-11-19

申请人： Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

发明人： Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

IPC分类号： G01N21/00

CPC分类号： H01L22/12

摘要： A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.

摘要翻译： 公开了一种形成装置的方法。 该方法包括提供衬底并在衬底上处理器件的一层。 该层用检查工具检查缺陷。 检查工具用从在已知位置处编程到层中的缺陷来确定的检查配方来编程。

公开(公告)号：US08178417B2

公开(公告)日：2012-05-15

申请号：US12107751

申请日：2008-04-22

申请人： Shailendra Mishra ,  James Yong Meng Lee ,  Zhao Lun ,  Wen Zhi Gao ,  Chung Woh Lai ,  Huang Liu ,  Johnny Widodo ,  Liang Choo Hsia

发明人： Shailendra Mishra ,  James Yong Meng Lee ,  Zhao Lun ,  Wen Zhi Gao ,  Chung Woh Lai ,  Huang Liu ,  Johnny Widodo ,  Liang Choo Hsia

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.

摘要翻译： 公开了一种使用多步蚀刻工艺形成浅沟槽隔离（STI）结构的方法。 通过以比掩模层更高的蚀刻速率选择性地蚀刻衬底来进行第一蚀刻步骤，以形成具有陡峭锥角的预备开口。 第二蚀刻步骤是通过非选择性蚀刻衬底来加深初步开口以形成具有基本平坦底部的STI间隙。

公开(公告)号：US20120074537A1

公开(公告)日：2012-03-29

申请号：US12888434

申请日：2010-09-23

申请人： Sung Mun JUNG ,  Swee Tuck WOO ,  Sanford CHU ,  Liang Choo HSIA

发明人： Sung Mun JUNG ,  Swee Tuck WOO ,  Sanford CHU ,  Liang Choo HSIA

IPC分类号： H01L29/51 ,  H01L21/31 ,  H01L21/66

CPC分类号： H01L29/511 ,  H01L21/02326 ,  H01L21/28282 ,  H01L22/12 ,  H01L22/20 ,  H01L29/792

摘要： A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.

摘要翻译： 公开了一种形成装置的方法。 该方法包括提供衬底并在具有成形厚度TFD的衬底上形成器件层。 在具有成形厚度TFC的基板上形成覆盖层。 形成覆盖层消耗所需量的器件层，以使器件层的厚度达到目标厚度TTD。 将覆盖层的厚度从TFC调整到大约目标厚度TTC。

公开(公告)号：US08102054B2

公开(公告)日：2012-01-24

申请号：US12860946

申请日：2010-08-23

申请人： Bei Chao Zhang ,  Chim Seng Seet ,  Juan Boon Tan ,  Fan Zhang ,  Yong Chiang Ee ,  Bo Tao ,  Tong Qing Chen ,  Liang Choo Hsia

发明人： Bei Chao Zhang ,  Chim Seng Seet ,  Juan Boon Tan ,  Fan Zhang ,  Yong Chiang Ee ,  Bo Tao ,  Tong Qing Chen ,  Liang Choo Hsia

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L29/40

CPC分类号： H01L23/5329 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.

摘要翻译： 提出了一种形成半导体器件的方法。 该方法包括提供用其上形成的电介质层制备的衬底。 电介质层具有布置在电介质层上部的导线。 处理衬底以产生与导电线的顶表面不共面的电介质层的顶表面，以形成阶梯形状。

公开(公告)号：US20110316166A1

公开(公告)日：2011-12-29

申请号：US12825266

申请日：2010-06-28

申请人： Hong Yu ,  Huang Liu ,  Feng Zhao ,  Meisheng Zhou ,  Liang-Choo Hsia

发明人： Hong Yu ,  Huang Liu ,  Feng Zhao ,  Meisheng Zhou ,  Liang-Choo Hsia

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/7684

摘要： A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer.

摘要翻译： 集成电路系统的制造方法包括：在体基板上形成蚀刻停止层; 在所述蚀刻停止层上形成缓冲层; 在缓冲层上形成硬掩模; 通过所述蚀刻停止层形成穿透硅通孔，所述硬掩模被检测并且所述缓冲层以低的下压力去除; 以及在穿通硅通孔和蚀刻停止层上形成钝化层。

公开(公告)号：US07960283B2

公开(公告)日：2011-06-14

申请号：US12825325

申请日：2010-06-28

申请人： Jeff Jianhui Ye ,  Huang Liu ,  Alex K H See ,  Wei Lu ,  Hai Cong ,  Hui Peng Koh ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jeff Jianhui Ye ,  Huang Liu ,  Alex K H See ,  Wei Lu ,  Hai Cong ,  Hui Peng Koh ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/28 ,  H01L21/311

CPC分类号： H01L29/665 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/78

摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.

摘要翻译： 描述了在集成电路（IC）中形成硅化物触点的方法。 在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。 这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。 间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。