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公开(公告)号：US08797711B2
公开(公告)日：2014-08-05
申请号：US12632823
申请日：2009-12-08
IPC分类号： H01G4/228
摘要： A region where a plating film constituting an external electrode is formed can be accurately controlled in an electronic component in which the external electrode is formed by directly plating a particular region in a surface of a component body. In a component body, a bump is provided in a position in which a region where an external electrode should be formed is partitioned. In a plating process, growth of the plating film constituting the external electrode is substantially stopped or delayed in the bump. As a result, a termination point of the growth of the plating film constituting the external electrode can be accurately controlled in the position of the bump.
摘要翻译： 在形成外部电极的电子部件中，通过直接对构成体的表面的特定区域进行电镀，能够精确地控制形成有构成外部电极的镀膜的区域。 在构成体中，在形成有外部电极的区域被分隔的位置设置凸块。 在电镀工艺中，构成外部电极的镀膜的生长在凸块中基本上停止或延迟。 结果，可以在凸块的位置上精确地控制构成外部电极的镀膜的生长终止点。
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公开(公告)号：US08730646B2
公开(公告)日：2014-05-20
申请号：US12466435
申请日：2009-05-15
摘要： A laminated electronic component includes outer terminal electrodes including lower plating films including metal particles having an average size of 0.5 μm or less, the lower plating films being formed by directly plating an outer surface of an electronic component body such that the lower plating films are electrically connected to exposed portions of inner conductors. The outer terminal electrodes may further include upper plating films formed on the lower plating films, the upper plating films being defined by one or more layers. Metal particles defining the upper plating films may have an average size of 0.5 μm or less. The metal particles defining the lower plating films may be Cu particles.
摘要翻译： 层叠电子部件包括外部端子电极，其包括具有平均尺寸为0.5μm以下的金属粒子的下部电镀膜，下部电镀膜通过直接电镀电子部件主体的外表面而形成，使得下部电镀膜为电气 连接到内部导体的暴露部分。 外部端子电极还可以包括形成在下部镀膜上的上部镀膜，上部镀膜由一层或多层限定。 限定上镀膜的金属粒子的平均粒径可以为0.5μm以下。 限定下镀层的金属颗粒可以是Cu颗粒。
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公开(公告)号：US08411409B2
公开(公告)日：2013-04-02
申请号：US13161535
申请日：2011-06-16
申请人： Makoto Ogawa , Akihiro Motoki , Masahito Saruban , Toshiyuki Iwanaga , Syunsuke Takeuchi , Kiyoyasu Sakurada
发明人： Makoto Ogawa , Akihiro Motoki , Masahito Saruban , Toshiyuki Iwanaga , Syunsuke Takeuchi , Kiyoyasu Sakurada
IPC分类号： H01G4/30
摘要： When an external terminal electrode of a ceramic electronic component such as a laminated ceramic capacitor is formed by plating, plating growth may be also caused even in an undesired location. The ceramic surface provided by a component main body is configured to include a high plating growth region of, for example, a barium titanate based ceramic, which exhibits relatively high plating growth, and a low plating growth region of, for example, a calcium zirconate based ceramic, which exhibits relatively low plating growth. The plating film constituting a first layer to define a base for an external terminal electrode is formed in such a way that the growth of a plated deposit deposited with conductive surfaces provided by exposed ends of internal electrodes as starting points is limited so as not to cross over a boundary between the high plating growth region and the low plating growth region toward the low plating growth region.
摘要翻译： 当通过电镀形成层压陶瓷电容器等陶瓷电子部件的外部端子电极时，即使在不希望的位置也可能产生电镀生长。 由组件主体提供的陶瓷表面被构造为包括例如呈现较高镀层生长的例如钛酸钡系陶瓷的高镀层生长区域和例如锆酸锆的低镀层生长区域 其具有相对较低的电镀生长。 构成用于限定外部端子电极的基底的第一层的电镀膜以这样的方式形成，使得以由内部电极的暴露端作为起点设置的导电表面沉积的镀覆沉积物的生长被限制为不交叉 在高电镀生长区域和低电镀生长区域之间的边界朝向低电镀生长区域。
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公开(公告)号：US20130062994A1
公开(公告)日：2013-03-14
申请号：US13411863
申请日：2012-03-05
申请人： Makoto OGAWA , Akihiro MOTOKI , Masahito SARUBAN , Wataru OGAWA
发明人： Makoto OGAWA , Akihiro MOTOKI , Masahito SARUBAN , Wataru OGAWA
CPC分类号： H01G4/30 , H01C7/13 , H01C7/18 , H01F17/0013 , H01F27/292 , H01G4/12 , H01G4/2325
摘要： A method for manufacturing a laminated ceramic electronic component enables formation of a plating film as at least a portion of an external electrode which connects exposed ends of internal electrodes. A component main body including a plurality of ceramic layers and a plurality of internal electrodes partially exposed from the component main body is prepared such that the component main body has a conductive region formed by diffusion of a conductive component included in the internal electrodes at the end surfaces of the ceramic layers located between adjacent exposed ends of the plurality of internal electrodes. The ceramic layers are preferably composed of a glass ceramic containing a glass component of about 10 weight % or more. A plating film is formed directly on the component main body by growing the exposed ends of the internal electrodes and the conductive region as nucleuses for plating deposition.
摘要翻译： 层叠陶瓷电子部件的制造方法能够形成作为连接内部电极的露出端的外部电极的至少一部分的电镀膜。 制备包括多个陶瓷层和从部件主体部分露出的多个内部电极的部件主体，使得部件主体具有由末端包括在内部电极中的导电部件的扩散形成的导电区域 位于多个内部电极的相邻的露出端之间的陶瓷层的表面。 陶瓷层优选由含有约10重量％以上的玻璃成分的玻璃陶瓷构成。 通过使内部电极和导电区域的露出端生长成电镀沉积的核，直接在部件主体上形成镀膜。
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公开(公告)号：US20120288724A1
公开(公告)日：2012-11-15
申请号：US13456326
申请日：2012-04-26
申请人： Makoto OGAWA , Akihiro MOTOKI , Atsuko SAITO , Kenji MASUKO , Toshinobu FUJIWARA
发明人： Makoto OGAWA , Akihiro MOTOKI , Atsuko SAITO , Kenji MASUKO , Toshinobu FUJIWARA
IPC分类号： B32B15/01
CPC分类号： C23C26/00 , C23C28/023 , H01G4/232 , H01G4/30 , Y10T428/31678
摘要： An electronic component that prevents or minimizes whiskers or has good solder wettability includes a rectangular solid-shaped electronic component element and external electrodes of terminal electrodes provided at opposed end surfaces of the electronic component element. First plated films including Ni are provided on the surfaces of the external electrodes. Second plated films including Sn defining an outermost layer are arranged so as to cover the first plated films. The second plated films have a polycrystalline structure, and flake-shaped Sn—Ni alloy grains are provided at a Sn crystal grain boundary. Intermetallic compound layers including Ni3Sn4 are provided at interfaces between the first plated films and the second plated films.
摘要翻译： 防止或最小化晶须或具有良好焊料润湿性的电子部件包括矩形固体形电子元件和设置在电子元件的相对端面处的端子电极的外部电极。 包括Ni的第一电镀膜设置在外部电极的表面上。 包括限定最外层的Sn的第二镀膜被布置成覆盖第一镀膜。 第二电镀膜具有多晶结构，并且在Sn晶粒边界处提供片状Sn-Ni合金晶粒。 包含Ni3Sn4的金属间化合物层设置在第一镀膜和第二镀膜之间的界面处。
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公开(公告)号：US20120161576A1
公开(公告)日：2012-06-28
申请号：US13315311
申请日：2011-12-09
申请人： Akihiro MOTOKI , Makoto OGAWA
发明人： Akihiro MOTOKI , Makoto OGAWA
摘要： In a method of manufacturing a laminate type electronic component, while the distance between adjacent exposed ends of a plurality of internal electrodes is adjusted preferably to be about 50 μm or less, a plurality of conductive particles composed of Pd, Pt, Cu, Au, or Ag are provided on the surface of a component main body. The conductive particles have an average particle size of about 0.1 nm to about 100 nm, which are distributed in island-shaped configurations over the entire surface of the component main body, while the average distance between the respective conductive particles is adjusted to fall within the range of about 10 nm to about 100 nm. The component main body is subjected to electrolytic plating such that plating growth develops in and around a region including the respective exposed ends of the plurality of internal electrodes.
摘要翻译： 在层压型电子部件的制造方法中，将多个内部电极的相邻的露出端之间的距离优选调整为约50μm以下，由Pd，Pt，Cu，Au， 或Ag设置在组件主体的表面上。 导电性粒子的平均粒径为约0.1nm〜约100nm，分布在成分主体的整个表面上的岛状构型，同时将各导电粒子之间的平均距离调节为 范围为约10nm至约100nm。 对组件主体进行电镀，使得电镀生长在包括多个内部电极的各个露出端的区域内和周围形成。
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7.发明授权公开(公告)号：US08154848B2
公开(公告)日：2012-04-10
申请号：US12354026
申请日：2009-01-15
摘要： A multilayer ceramic electronic component includes a laminate including a stack of a plurality of ceramic layers and a plurality of internal electrodes extending along interfaces between the ceramic layers, and a plurality of external electrodes electrically connecting the internal electrodes exposed at surfaces of the laminate. Each external electrode includes a plating layer at least at the portion directly connected to the internal electrodes. The plating layer has a compressive film stress of about 100 MPa or less or a tensile film stress of about 100 MPa or less.
摘要翻译： 多层陶瓷电子部件包括层叠体，其包括多个陶瓷层的叠层和沿着陶瓷层之间的界面延伸的多个内部电极，以及电连接在层叠体的表面露出的内部电极的多个外部电极。 每个外部电极至少包括直接连接到内部电极的部分的镀层。 镀层的压缩应力为约100MPa以下或拉伸膜应力为约100MPa以下。
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公开(公告)号：US20120058257A1
公开(公告)日：2012-03-08
申请号：US13295151
申请日：2011-11-14
IPC分类号： B05D5/12
CPC分类号： H01G4/008 , H01G4/005 , H01G4/2325 , Y10T29/417 , Y10T29/43 , Y10T29/435
摘要： A laminated electronic component is configured to include substrate plating films disposed on outer surfaces of an electronic component main body through direct plating such that external terminal electrodes are connected to exposed portions of internal conductors (internal electrodes), and the average particle diameter of metal particles defining the substrate plating film is at least about 1.0 μm. The external terminal electrode includes at least one layer of an upper plating film disposed on the substrate plating film. The metal particles defining the substrate plating film are Cu particles.
摘要翻译： 层叠电子部件被配置为包括通过直接电镀设置在电子部件主体的外表面上的基板镀膜，使得外部端子电极与内部导体（内部电极）的露出部分连接，金属粒子的平均粒径 限定衬底镀膜至少约1.0μm。 外部端子电极包括设置在基板镀膜上的至少一层上镀层。 限定衬底镀膜的金属颗粒是Cu颗粒。
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公开(公告)号：US20110234045A1
公开(公告)日：2011-09-29
申请号：US13050977
申请日：2011-03-18
申请人： Akihiro MOTOKI , Syunsuke TAKEUCHI , Makoto OGAWA , Seiichi NISHIHARA , Kenichi KAWASAKI , Shuji MATSUMOTO
发明人： Akihiro MOTOKI , Syunsuke TAKEUCHI , Makoto OGAWA , Seiichi NISHIHARA , Kenichi KAWASAKI , Shuji MATSUMOTO
CPC分类号： H01G4/248 , B32B18/00 , B32B37/18 , B32B2307/202 , B32B2315/02 , B32B2457/00 , C23C18/40 , H01G4/005 , H01G4/012 , H01G4/12 , H01G4/228 , H01G4/30
摘要： In a method of forming a plating layer for an external terminal electrode by applying, for example, copper plating to an end surface of a component main body with respective ends of internal electrodes exposed, and then applying a heat treatment at a temperature of about 1000° C. or more in order to improve the adhesion strength and moisture resistance of the external terminal electrode, the plating layer may be partially melted to decrease the bonding strength of the plating layer. In the step of applying a heat treatment at a temperature of about 1000° C. or more to a component main body with plating layers formed thereon, the average rate of temperature increase from room temperature to the temperature of about 1000° C. or more is set to about 100° C./minute or more. This average rate of temperature increase maintains a moderate eutectic state in the plating layer and ensures a sufficient bonding strength of the plating layer.
摘要翻译： 在形成外部端子电极用镀层的方法中，例如通过对内部电极的两端露出的部件主体的端面进行镀铜，然后在约1000℃的温度下进行热处理 ℃以上，为了提高外部端子电极的粘合强度和耐湿性，可以使镀层部分熔融，降低镀层的接合强度。 在其上形成有镀层的组件主体上，在约1000℃以上的温度下进行热处理的步骤中，平均温度从室温升高至约1000℃以上的温度 设定为约100℃/分钟以上。 该平均升温速率在镀层中保持中等的共晶状态，并确保镀层的充分的接合强度。
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公开(公告)号：US08018359B2
公开(公告)日：2011-09-13
申请号：US12753784
申请日：2010-04-02
IPC分类号： H03M7/46
CPC分类号： H03M7/42
摘要： Various embodiments are provided to reduce a processing time taken when plural bit lengths each assigned to plural strings are converted into plural codes. In one exemplary embodiment, in response to input of the plurality of bit lengths, a number of strings assigned each of the bit lengths, a bit length assigned to each of the strings, and a sequence number of each string in a group of strings assigned each of the bit lengths are recorded. A plurality of base codes are generated on the basis of the numbers of the strings recorded by the recording unit, the base codes each being a code used as a base for codes having the same one of the bit lengths. A plurality of codes is generated by performing in parallel a plurality of processes respectively for the plurality of strings.
摘要翻译： 提供了各种实施例，以减少每个分配给多个字符串的多个位长度被转换成多个代码所需的处理时间。 在一个示例性实施例中，响应于多个比特长度的输入，分配每个比特长度的字符串的数量，分配给每个字符串的比特长度以及被分配的一组字符串中的每个字符串的序列号 记录每个位长度。 基于由记录单元记录的串的数量生成多个基本码，每个基准码是用作具有相同比特长度的码的基础的码。 通过分别并行地执行多个字符串来生成多个代码。
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