公开(公告)号：US07011531B2

公开(公告)日：2006-03-14

申请号：US11031859

申请日：2005-01-07

Applicant: Frank D. Egitto ,  Keith J. Miller ,  Manh-Quan T. Nguyen

Inventor： Frank D. Egitto ,  Keith J. Miller ,  Manh-Quan T. Nguyen

IPC: H01R12/00

CPC classification number: G01R1/06733 ,  G01R1/0735 ,  H01R12/52 ,  H01R12/7082 ,  H01R12/714 ,  H01R2201/20 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/09845 ,  H05K2201/10378 ,  H05K2203/0369 ,  H05K2203/0733 ,  Y10T29/4922

Abstract: A structure and method to establish an electrical connection between a tester and an electrical component. A flexible dielectric layer has a first side and a second side. A through via extends through the first side and the second side of the dielectric layer. A blind via is placed in a position that is offset from the through via and extends laterally in a first direction from a section of the first through via to a section of the flexible dielectric layer. The blind via extends in a second direction from the first side of the flexible dielectric layer to a section of the flexible dielectric layer that is between the first side and the second side of the dielectric layer. An electrically conductive member extends through the through via and extends into the blind via, thereby filling the through via and the blind via. The electrically conductive member has a first surface and a second surface. Any distance between the first surface and the second surface is greater than a distance between the first side of the dielectric layer and the second side of the dielectric layer.

Abstract translation: 一种在测试仪和电气部件之间建立电气连接的结构和方法。 柔性介电层具有第一面和第二面。 通孔延伸穿过电介质层的第一侧和第二侧。 盲通孔放置在从通孔偏移的位置，并且在从第一通孔的一部分到柔性介电层的一部分的第一方向上横向延伸。 盲孔从柔性介电层的第一侧沿第二方向延伸到介电层的第一侧和第二侧之间的柔性介电层的一部分。 导电构件延伸穿过通孔并延伸到盲孔中，从而填充通孔和盲孔。 导电构件具有第一表面和第二表面。 第一表面和第二表面之间的任何距离都大于电介质层的第一面和电介质层的第二面之间的距离。

公开(公告)号：US06881072B2

公开(公告)日：2005-04-19

申请号：US10263510

申请日：2002-10-01

Applicant: Frank D. Egitto ,  Keith J. Miller ,  Manh-Quan T. Nguyen

Inventor： Frank D. Egitto ,  Keith J. Miller ,  Manh-Quan T. Nguyen

IPC: G01R1/067 ,  G01R1/073 ,  H05K3/20 ,  H05K3/40 ,  H05K3/42 ,  H01R12/00

CPC classification number: G01R1/06733 ,  G01R1/0735 ,  H01R12/52 ,  H01R12/7082 ,  H01R12/714 ,  H01R2201/20 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/09845 ,  H05K2201/10378 ,  H05K2203/0369 ,  H05K2203/0733 ,  Y10T29/4922

Abstract: A structure and method to establish an electrical connection between a tester and an electrical component. A flexible dielectric layer has a first side and a second side. A through via extends through the first side and the second side of the dielectric layer. A blind via is placed in a position that is offset from the through via and extends laterally in a first direction from a section of the first through via to a section of the flexible dielectric layer. The blind via extends in a second direction from the first side of the flexible dielectric layer to a section of the flexible dielectric layer that is between the first side and the second side of the dielectric layer. An electrically conductive member extends through the through via and extends into the blind via, thereby filling the through via and the blind via. The electrically conductive member has a first surface and a second surface. Any distance between the first surface and the second surface is greater than a distance between the first side of the dielectric layer and the second side of the dielectric layer.

公开(公告)号：US06790305B2

公开(公告)日：2004-09-14

申请号：US10266652

申请日：2002-10-08

Applicant: Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

Inventor： Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

IPC: B32B3114

CPC classification number: H01L21/486 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/061 ,  H05K2203/1152 ,  Y10S438/976 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804 ,  Y10T428/2839 ,  Y10T428/2848

Abstract: A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

Abstract translation: 一种用于在印刷电路板和各种电子封装上施加介电材料层的小间距z轴电互连的方法。 一种用于平行制造中间结构的方法，其随后连接以形成最终结构。 此外，提供了一种采用诸如树脂涂覆铜之类的介电材料的z互连电结构，可用于制造包括印刷线路板（PWB），基板，多芯片模块等的各种类型的电子封装。

公开(公告)号：US06955849B2

公开(公告)日：2005-10-18

申请号：US10854598

申请日：2004-05-26

Applicant: Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

Inventor： Brian E. Curcio ,  Frank D. Egitto ,  Robert M. Japp ,  Thomas R. Miller ,  Manh-Quan T. Nguyen ,  Douglas O. Powell

IPC: H01L21/48 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00 ,  B32B7/12

CPC classification number: H01L21/486 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/061 ,  H05K2203/1152 ,  Y10S438/976 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804 ,  Y10T428/2839 ,  Y10T428/2848

Abstract: A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

Abstract translation: 一种用于在印刷电路板和各种电子封装上施加介电材料层的小间距z轴电互连的方法。 一种用于平行制造中间结构的方法，其随后连接以形成最终结构。 此外，提供了一种采用诸如树脂涂覆铜之类的介电材料的z互连电结构，可用于制造包括印刷线路板（PWB），基板，多芯片模块等的各种类型的电子封装。

公开(公告)号：US06518516B2

公开(公告)日：2003-02-11

申请号：US10121821

申请日：2002-04-11

Applicant: Kim J. Blackwell ,  Frank D. Egitto ,  Voya R. Markovich ,  Manh-Quan T. Nguyen ,  Douglas O. Powell ,  David L. Thomas

Inventor： Kim J. Blackwell ,  Frank D. Egitto ,  Voya R. Markovich ,  Manh-Quan T. Nguyen ,  Douglas O. Powell ,  David L. Thomas

IPC: H01K909

CPC classification number: H01L23/50 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/3025 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A multilayered laminate, substructures and associated methods of fabrication are presented. The multilayered laminate includes in sequential order: (a) a first intermediate layer having microvias and conductive lands; (b) a plurality of signal/power plane substructures, wherein a dielectric material of an intervening dielectric layer insulatively separates each pair of successive signal/power plane substructures and (c) a second intermediate layer having microvias and conductive lands.