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    Process for producing semiconductor devices by self-alignment technology
    2.
    发明授权
    Process for producing semiconductor devices by self-alignment technology 失效
    通过自对准技术制造半导体器件的工艺

    公开(公告)号：US4845046A

    公开(公告)日：1989-07-04

    申请号：US91609

    申请日：1987-08-31

    申请人： Masafumi Shimbo

    发明人： Masafumi Shimbo

    IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/285 ,  H01L21/32 ,  H01L21/331 ,  H01L21/336 ,  H01L21/338 ,  H01L29/417 ,  H01L29/732 ,  H01L29/772 ,  H01L29/78 ,  H01L29/812

    CPC分类号： H01L29/66606 ,  H01L21/033 ,  H01L21/28525 ,  H01L21/32 ,  H01L29/41775 ,  H01L29/66272 ,  H01L29/7722 ,  H01L29/78

    摘要： A method of manufacturing semiconductor device wherein the self-alignment technique is employed to simplify the manufacturing process and includes the steps of successively depositing multiple layer masking films comprising a first, a second and a third masking films on an n-type Si region, forming an island region of the multiple layer films and a peripheral portion of the second masking film which is etched away, by side-etching, from the edges of the other masking films, selectively forming an oxidized film, selectively etching the first oxidized film using the second masking film as a mask and forming fine contact windows between the selectively formed oxidized film and the first masking film, depositing a semiconductor thin film, lifting-off the semiconductor thin film by removing the second and third masking films and leaving a portion of the semiconductor film which contacts the windows, oxidizing the surface of the semiconductor thin film and removing the first masking film.

    摘要翻译： 一种制造半导体器件的方法，其中使用自对准技术来简化制造工艺，并且包括以下步骤：在n型Si区域上依次沉积包括第一，第二和第三掩模膜的多层掩模膜，形成 多层膜的岛区域和通过从其它掩模膜的边缘侧蚀刻而被蚀刻掉的第二掩模膜的周边部分，选择性地形成氧化膜，使用所述第一氧化膜选择性地蚀刻第一氧化膜 第二掩模膜作为掩模，并且在选择性地形成的氧化膜和第一掩模膜之间形成微细的接触窗，沉积半导体薄膜，通过去除第二和第三掩模膜并留下一部分 半导体膜，其与窗口接触，氧化半导体薄膜的表面并除去第一掩模膜。

    Method of fabricating MOS field effect transistor
    3.
    发明授权
    Method of fabricating MOS field effect transistor 失效
    制造MOS场效应晶体管的方法

    公开(公告)号：US4838993A

    公开(公告)日：1989-06-13

    申请号：US128088

    申请日：1987-12-03

    申请人： Kenji Aoki ,  Masafumi Shimbo

    发明人： Kenji Aoki ,  Masafumi Shimbo

    IPC分类号： B82B1/00 ,  H01L21/20 ,  H01L21/203 ,  H01L21/336 ,  H01L29/08 ,  H01L29/36 ,  H01L29/78

    CPC分类号： H01L29/66636 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/78 ,  H01L29/7834 ,  Y10S148/05

    摘要： A novel MOS field effect transistor which operates at high speed and with low power consumption has impurity doped source and drain regions deposited at 850.degree. C. or less by molecular layer epitaxial growth method. The molecular layer epitaxial growth is concurrently carried out with the control of impurity doping concentration so that the layers epitaxially deposited has a lightly doped region and a heavily doped region. Since the thickness of the growth layer can be controlled with a degree of accuracy on the order of an atom layer and thermal diffusions can remarkably be reduced by the low deposition temperature, an overlap of a gate over each of the source and drain regions can be reduced to 500 .ANG. or less.

    摘要翻译： 一种以高速和低功耗工作的新型MOS场效应晶体管通过分子层外延生长法在850℃或更低温度下沉积杂质掺杂源极和漏极区。 通过控制杂质掺杂浓度同时进行分子层外延生长，使得外延沉积的层具有轻掺杂区域和重掺杂区域。 由于生长层的厚度可以以原子层的顺序精度控制，并且通过低沉积温度可以显着降低热扩散，所以源极和漏极区域之间的栅极的重叠可以是 降至500 ANGSTROM以下。

    Method of manufacturing an integrated circuit device having vertical field effect transistors
    5.
    发明授权
    Method of manufacturing an integrated circuit device having vertical field effect transistors 失效
    制造具有垂直场效应晶体管的集成电路器件的方法

    公开(公告)号：US4449284A

    公开(公告)日：1984-05-22

    申请号：US183064

    申请日：1980-09-02

    申请人： Masafumi Shimbo

    发明人： Masafumi Shimbo

    IPC分类号： H01L21/306 ,  H01L27/02 ,  H01L29/10 ,  H01L29/739 ,  H01L21/95

    CPC分类号： H01L21/30608 ,  H01L27/0225 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/739

    摘要： A method of manufacturing an integrated circuit device including vertical static induction transistors (SIT) having a first recess between the gate region and the drain (or source) region to reduce the capacitance between both regions and a second recess on an outer surface of the SIT gate to reduce the gate capacitance and a minority carrier storage. The method includes the steps of removing a masking film on the SIT channel region while leaving the masking film at the portions of the gate region and the drain region; forming the first and the second recesses in the channel region; locally oxidizing the exposed channel region; and forming the gate region and the drain region by removing the masking film.

    摘要翻译： 一种制造包括垂直静电感应晶体管（SIT）的集成电路器件的方法，所述垂直静电感应晶体管（SIT）在所述栅极区域和所述漏极（或源极）区域之间具有第一凹陷，以减小所述两个区域之间的电容和所述SIT的外表面上的第二凹陷 栅极减少栅极电容和少数载流子存储。 该方法包括以下步骤：在掩模膜位于栅极区域和漏极区域的部分处，去除SIT沟道区上的掩模膜; 在通道区域中形成第一和第二凹槽; 局部氧化暴露的通道区域; 并通过去除掩模膜形成栅区和漏区。

    Method for fabricating semiconductor devices
    6.
    发明授权
    Method for fabricating semiconductor devices 失效
    制造半导体器件的方法

    公开(公告)号：US4380481A

    公开(公告)日：1983-04-19

    申请号：US244793

    申请日：1981-03-17

    申请人： Masafumi Shimbo

    发明人： Masafumi Shimbo

    IPC分类号： H01L29/80 ,  H01L21/033 ,  H01L21/32 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/808

    CPC分类号： H01L21/32 ,  H01L21/033 ,  H01L21/76213 ,  H01L29/8083 ,  Y10S438/911

    摘要： A method of fabricating a semiconductor device comprising forming an island-shaped multi-layered structure of oxides and nitrides on the surface of a semiconductor. The multi-layered structure is selectively etched to define diffusion windows for forming a semiconductor structure in the semiconductor surface having a central region of one conductivity type surrounded by another region of a different conductivity type. A second island-like multi-layered structure is formed and is etched for controlling the duration of the etching steps by controlling the amount that the masks lift off from the insulation layers subjected to etching. The etching is carried out by side etching.

    摘要翻译： 一种制造半导体器件的方法，包括在半导体的表面上形成氧化物和氮化物的岛状多层结构。 选择性地蚀刻多层结构以限定在具有由不同导电类型的另一区域包围的一种导电类型的中心区域的半导体表面中形成半导体结构的扩散窗口。 形成第二岛状多层结构，并通过控制掩模从经受蚀刻的绝缘层剥离的量来蚀刻以控制蚀刻步骤的持续时间。 蚀刻通过侧面蚀刻进行。

    Method of making a CMOS device with trench isolation device
    7.
    发明授权
    Method of making a CMOS device with trench isolation device 失效
    制造具有沟槽隔离器件的CMOS器件的方法

    公开(公告)号：US4980306A

    公开(公告)日：1990-12-25

    申请号：US265698

    申请日：1988-11-01

    申请人： Masafumi Shimbo

    发明人： Masafumi Shimbo

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L29/78

    CPC分类号： H01L21/76237 ,  H01L21/76224 ,  H01L21/823878

    摘要： A semiconductor device of the complementary metal-insulator semiconductor type is composed of a pair of N-type metal oxide semiconductor transistor formed on a P-type silicon substrate and P-type metal oxide semiconductor transistor formed on an n-type well disposed within the p-type substrate. An isolation tranch is disposed between the pair of adjacent transistors, and has one sidewall bordering the well, another opposed sidewall bordering the substrate, and a bottom wall. A selective epitaxial film of p-type is selectively epitaxially deposited on the sidewalls and bottom wall of the trench. The epitaxial film has a dopant density greater than that of the substrate. An insulation oxide material is filled within the trench so as to effectively isolate the pair of transistors from each other.

    摘要翻译： 互补金属 - 绝缘体半导体型的半导体器件由形成在P型硅衬底上的一对N型金属氧化物半导体晶体管和形成在n型阱中的n型阱构成的P型金属氧化物半导体晶体管构成 p型基板。 在一对相邻的晶体管之间设置有一个隔离放电线，并且具有一个侧壁与该阱连接，另一个相对的侧壁与该基板接合，一个底壁。 p型的选择性外延膜被选择性地外延沉积在沟槽的侧壁和底壁上。 外延膜的掺杂密度大于衬底的掺杂密度。 绝缘氧化物材料填充在沟槽内，以便有效地将一对晶体管彼此隔离。

    Method of fabricating an insulated gate semiconductor device having a self-aligned gate
    8.
    发明授权
    Method of fabricating an insulated gate semiconductor device having a self-aligned gate 失效
    制造具有自对准栅极的绝缘栅半导体器件的方法

    公开(公告)号：US4939154A

    公开(公告)日：1990-07-03

    申请号：US172029

    申请日：1988-03-23

    申请人： Masafumi Shimbo

    发明人： Masafumi Shimbo

    IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/66606 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/78

    摘要： The present invention provides a fabrication method of miniature insulated gate semiconductor devices such as MOS and CMOS in which their gates are formed by self-alignment, and in addition, provision of lightly doped drain (LDD) structure is easy. Therefore the present invention is extremely effective in the fabrication of miniature semiconductor devices which can be highly integrated and can operate at high speed.

    摘要翻译： 本发明提供了通过自对准形成其栅极的诸如MOS和CMOS的微型绝缘栅极半导体器件的制造方法，此外，提供轻掺杂漏极（LDD）结构容易。 因此，本发明在可以高度集成并且可以高速运行的微型半导体器件的制造中非常有效。