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    BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS
    2.
    发明申请
    BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS 有权
    具有多个发光指示器的双极接头晶体管

    公开(公告)号：US20130119508A1

    公开(公告)日：2013-05-16

    申请号：US13294671

    申请日：2011-11-11

    申请人： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

    发明人： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

    IPC分类号： H01L29/73 ,  G06F17/50 ,  H01L21/331

    CPC分类号： H01L29/66303 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/7322 ,  H01L29/735

    摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.

    摘要翻译： 用于制造双极结型晶体管的方法，双极结型晶体管以及用于双极结型晶体管的设计结构。 双极结晶体管可以包括布置在不同的发射极指中的多个发射极。 形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。 发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。 发射极延伸通过外部基极层和硅化物层与本征基极层接触。 发射器可以在替代型工艺中使用牺牲发射器基座形成。

    Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure
    5.
    发明授权
    Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure 有权
    集成电路包括绝缘体上绝缘体上的晶体管结构，相关方法和设计结构

    公开(公告)号：US09041105B2

    公开(公告)日：2015-05-26

    申请号：US13553947

    申请日：2012-07-20

    申请人： William F. Clark, Jr. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    发明人： William F. Clark, Jr. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L21/265

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

    摘要翻译： 一种集成电路（IC）及其制造方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

    PNP bipolar junction transistor fabrication using selective epitaxy
    6.
    发明授权
    PNP bipolar junction transistor fabrication using selective epitaxy 有权
    PNP双极结晶体管制造使用选择性外延

    公开(公告)号：US08921194B2

    公开(公告)日：2014-12-30

    申请号：US13294697

    申请日：2011-11-11

    申请人： David L. Harame ,  Qizhi Liu

    发明人： David L. Harame ,  Qizhi Liu

    IPC分类号： H01L21/331 ,  H01L21/8228 ,  H01L21/8224 ,  H01L29/66 ,  H01L27/082 ,  H01L29/737 ,  H01L29/10

    CPC分类号： H01L29/735 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/16 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/7371

    摘要： Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.

    摘要翻译： 横向PNP双极结晶体管，用于制造横向PNP双极结型晶体管的方法，以及横向PNP双极结型晶体管的设计结构。 横向PNP双极结晶体管的发射极和集电极由通过选择性外延生长工艺形成的p型半导体材料组成。 源极和漏极各自直接接触用于形成发射极和集电极的器件区域的顶表面。 基部触点可以形成在顶表面上并且覆盖限定在器件区域内的n型基极。 发射极通过基座触点与收集器横向分开。 另一个基底接触可以形成在由基部与另一个基部接触分离的器件区域中。

    LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION
    7.
    发明申请
    LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION 有权
    用于包括自对准发射极区域的双极晶体管的本地布线

    公开(公告)号：US20140021587A1

    公开(公告)日：2014-01-23

    申请号：US13551971

    申请日：2012-07-18

    申请人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

    发明人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

    IPC分类号： H01L29/66 ,  H01L29/73

    CPC分类号： H01L29/66234 ,  H01L29/0804 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/732

    摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

    摘要翻译： 本发明的方面提供了一种自对准发射极的双极晶体管。 在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间​​形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。

    TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE
    8.
    发明申请
    TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE 审中-公开
    晶体管和形成晶体管的方法具有降低的基极电阻

    公开(公告)号：US20120313146A1

    公开(公告)日：2012-12-13

    申请号：US13155730

    申请日：2011-06-08

    申请人： Marc W. Cantell ,  Thai Doan ,  Jessica A. Levy ,  Qizhi Liu ,  William J. Murphy ,  Christa R. Willets

    发明人： Marc W. Cantell ,  Thai Doan ,  Jessica A. Levy ,  Qizhi Liu ,  William J. Murphy ,  Christa R. Willets

    IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L29/73

    CPC分类号： H01L29/66234 ,  H01L21/8222 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

    摘要： Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.

    摘要翻译： 公开了一种晶体管结构，具有完全硅化的外基，用于降低碱电阻Rb。 具体地说，金属硅化物层覆盖外部基体，包括在T形发射体的上部下方延伸的外部基底部分。 用于确保金属硅化物层覆盖外部基极的这一部分的一个示例性技术需要使发射极的上部逐渐变细。 这种锥形允许在处理期间完全去除发射器上部下方的牺牲层，从而将外部基底暴露在下面，并使硅化物所需的金属层沉积在其上。 例如，可以使用高压溅射技术来沉积该金属层，以确保外部基底的所有暴露表面，甚至覆盖在发射体上部以下的那些。

    TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR
    9.
    发明申请
    TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR 有权
    具有侧向定义的内部基极到极端基底连接区域的晶体管结构和形成晶体管的方法

    公开(公告)号：US20110312147A1

    公开(公告)日：2011-12-22

    申请号：US12967268

    申请日：2010-12-14

    申请人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

    发明人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

    IPC分类号： H01L21/331

    CPC分类号： H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

    摘要： Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

    摘要翻译： 公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。 晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定的导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是 随后形成。 可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。

    Method of base formation in a BiCMOS process
    10.
    发明授权
    Method of base formation in a BiCMOS process 有权
    BiCMOS工艺中碱形成的方法

    公开(公告)号：US07625792B2

    公开(公告)日：2009-12-01

    申请号：US10599938

    申请日：2005-04-06

    申请人： Peter J. Geiss ,  Alvin J. Joseph ,  Qizhi Liu ,  Bradley A. Orner

    发明人： Peter J. Geiss ,  Alvin J. Joseph ,  Qizhi Liu ,  Bradley A. Orner

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/0804 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

    摘要： Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

    摘要翻译： 公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极，集电极之上的本征基极，与集电极相邻的浅沟槽隔离区，在本征基极之上的凸起的外部基极，T形发射极 在外部基极之上，邻近发射极的间隔物和通过间隔物与发射极分离的硅化物层。