Contact magnetic transfer template
    1.
    发明授权
    Contact magnetic transfer template 失效
    接触磁性传递模板

    公开(公告)号:US07572499B2

    公开(公告)日:2009-08-11

    申请号:US11044777

    申请日:2005-01-26

    摘要: A contact magnetic transfer (CMT) master template has a flexible plastic film with a planarized top or upper surface containing magnetic islands separated from one another by nonmagnetic regions. The flexible plastic film is secured at its perimeter to a silicon annulus that provides rigid support at the perimeter of the film. The plastic film is preferably polyimide that has recesses filled with the magnetic material that form the pattern of magnetic islands. The upper surfaces of the islands and the upper surfaces of the nonmagnetic regions form a continuous planar surface. The nonmagnetic regions are formed of chemical-mechanical-polishing (CMP) stop layer material that remains after a CMP process has planarized the upper surface of the plastic film.

    摘要翻译: 接触磁传递(CMT)主模板具有柔性塑料膜,其具有包含通过非磁性区域彼此分离的磁岛的平坦化顶部或上部表面。 柔性塑料膜在其周边固定在硅环上,该硅环在膜的周边提供刚性支撑。 塑料膜优选为具有填充有形成磁岛图案的磁性材料的凹部的聚酰亚胺。 岛的上表面和非磁性区的上表面形成连续的平坦表面。 非磁性区域由化学机械抛光(CMP)阻挡层材料形成,其在CMP工艺已经使塑料膜的上表面平坦化之后残留。

    Method for making a contact magnetic transfer template
    2.
    发明授权
    Method for making a contact magnetic transfer template 失效
    制造接触磁传输模板的方法

    公开(公告)号:US07160477B2

    公开(公告)日:2007-01-09

    申请号:US11044288

    申请日:2005-01-26

    IPC分类号: B44C1/22

    摘要: A contact magnetic transfer (CMT) master template is made by first adhering a plastic film to a first surface of a silicon wafer. A resist pattern is then formed on the polyimide film and the polyimide is reactive-ion-etched through the resist to form recesses. The resist is removed and a chemical-mechanical-polishing (CMP) stop layer is deposited over the non-recessed regions of the polyimide, and optionally into the bottoms of the recesses. A layer of magnetic material is then deposited over the polyimide film to fill the recesses. A CMP process is then performed to remove magnetic material above the recesses and above the non-recessed regions and continued until the CMP stop layer is reached. The resulting upper surface of the polyimide film is then a continuous planar film of magnetic islands and regions of CMP stop layer material that function as the nonmagnetic regions of the template.

    摘要翻译: 通过首先将塑料膜粘附到硅晶片的第一表面上来制造接触磁传递(CMT)主模板。 然后在聚酰亚胺膜上形成抗蚀剂图案,并通过抗蚀剂反应离子蚀刻聚酰亚胺以形成凹陷。 去除抗蚀剂,并在化学机械抛光(CMP)停止层上沉积在聚酰亚胺的非凹陷区域上,并且任选地沉积到凹部的底部中。 然后将一层磁性材料沉积在聚酰亚胺膜上以填充凹部。 然后执行CMP处理以除去凹部上方的磁性材料并且在非凹陷区域上方并继续直到达到CMP停止层。 所得到的聚酰亚胺膜的上表面是磁性岛的连续平面膜和作为模板的非磁性区域的CMP停止层材料的区域。

    A p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors
    6.
    发明申请
    A p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors 有权
    具有应变纳米线通道和嵌入式SiGe源极和漏极应力的p-FET

    公开(公告)号:US20120280211A1

    公开(公告)日:2012-11-08

    申请号:US13554065

    申请日:2012-07-20

    IPC分类号: H01L29/775

    摘要: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

    摘要翻译: 提供了在纳米级基于沟道的场效应晶体管(FET)中嵌入硅锗(e-SiGe)源极和漏极应力的技术。 一方面,制造FET的方法包括以下步骤。 提供其上具有电介质的掺杂衬底。 在电介质上放置至少一个硅(Si)纳米线。 掩模纳米线的一个或多个部分,使纳米线的其它部分暴露出来。 外延锗(Ge)生长在纳米线的暴露部分上。 外延Ge与纳米线中的Si相互扩散以形成纳米线中嵌入纳米线中的压应变的SiGe区域。 掺杂衬底用作FET的栅极,纳米线的掩蔽掉的部分用作FET的沟道,并且嵌入的SiGe区域用作FET的源极和漏极区域。