公开(公告)号：US08895445B2

公开(公告)日：2014-11-25

申请号：US13228108

申请日：2011-09-08

申请人： Wen-Kuo Hsieh ,  Marowen Ng ,  Ming-Chung Liang ,  Hsin-Yi Tsai

发明人： Wen-Kuo Hsieh ,  Marowen Ng ,  Ming-Chung Liang ,  Hsin-Yi Tsai

IPC分类号： H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

摘要： A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.

摘要翻译： 用于形成衬底上的互连结构的通路和沟槽的方法包括通过光刻胶层中的节距减小图案曝光，显影图案以去除通孔间距减小图案，使用聚合物气体部分地蚀刻光致抗蚀剂层以将图案重新形成为 小通孔形状，并蚀刻剩余的光致抗蚀剂层以延伸重塑图案。 重新成形的小通孔形状图案具有比在长方向上的通孔间距减小图案更小的间距。 对于具有每个具有两个通孔的通孔间距减小图案，图案具有花生形状。 在重新成形蚀刻操作期间，聚合物气体更多地沉积在夹入的中间部分中，同时允许在未切割的部分中进行向下蚀刻。

公开(公告)号：US20110070738A1

公开(公告)日：2011-03-24

申请号：US12873429

申请日：2010-09-01

申请人： Ming-Chung LIANG ,  Chih-Hao CHEN ,  Yu-Yu CHEN ,  Hsin-Yi TSAI

发明人： Ming-Chung LIANG ,  Chih-Hao CHEN ,  Yu-Yu CHEN ,  Hsin-Yi TSAI

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0338 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816

摘要： A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.

摘要翻译： 光刻图案的方法包括在材料层上形成硬掩模层，并在硬掩模层上形成覆盖层。 在光刻胶灰化过程中，封盖层不与氧气反应。 通过使用第一抗蚀剂图案和第二抗蚀剂图案作为蚀刻掩模来对覆盖层进行图案化。 在图案化覆盖层之后，通过使用图案化覆盖层作为蚀刻掩模来对硬掩模层进行图案化。

公开(公告)号：US20100308469A1

公开(公告)日：2010-12-09

申请号：US12478619

申请日：2009-06-04

申请人： Hsin-Yi Tsai ,  Chih-Hao Chen ,  Ming-Chung Liang ,  Chii-Ping Chen ,  Lai Chien Wen ,  Yuh-Jier Mii

发明人： Hsin-Yi Tsai ,  Chih-Hao Chen ,  Ming-Chung Liang ,  Chii-Ping Chen ,  Lai Chien Wen ,  Yuh-Jier Mii

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.

摘要翻译： 本公开提供一种半导体器件，其包括：衬底; 第一导电线，位于所述衬底上并且沿着第一轴线延伸，所述第一导电线具有第一长度和第一宽度，所述第一长度沿着所述第一轴线被测量; 第二导电线，位于第一导电线之上并沿着不同于第一轴的第二轴延伸，第二导线具有第二长度和第二宽度，第二长度沿第二轴线测量; 以及耦合所述第一和第二导线的通孔，所述通孔具有接触所述第二导电线的上表面和接触所述第一导线的下表面。 通孔在上表面具有大致直边，直边沿第二轴线延伸并与第二导线基本对准。

公开(公告)号：US20080311756A1

公开(公告)日：2008-12-18

申请号：US11764053

申请日：2007-06-15

申请人： Chih-Hao Chen ,  Chia-Cheng Chou ,  Ming-Chung Liang ,  Keng-Chu Lin ,  Tzu-Li Lee

发明人： Chih-Hao Chen ,  Chia-Cheng Chou ,  Ming-Chung Liang ,  Keng-Chu Lin ,  Tzu-Li Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/31138

摘要： A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.

摘要翻译： 提供了一种通过降低RC延迟时间来提高集成电路性能的系统和方法。 优选的实施方案包括在低k电介质蚀刻之后向灰/冲击等离子体工艺中添加反应性蚀刻气体。 说明性实施例实现了在低k电介质蚀刻期间形成的损伤层的去除。

公开(公告)号：US07303995B2

公开(公告)日：2007-12-04

申请号：US10465850

申请日：2003-06-20

申请人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

发明人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

IPC分类号： H01L21/311 ,  H01L21/302

CPC分类号： G03F7/405 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338

摘要： A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.

摘要翻译： 一种半导体制造方法，其包括提供衬底，在所述衬底上提供材料层，在所述材料层上提供光致抗蚀剂层，图案化和限定所述光致抗蚀剂层，在所述图案化和限定的光致抗蚀剂层上沉积聚合物层，其中 聚合物层是共形和不敏感的，并且蚀刻聚合物层和材料层。

公开(公告)号：US06601596B2

公开(公告)日：2003-08-05

申请号：US09847200

申请日：2001-05-02

申请人： Ming-Chung Liang ,  Shin-Yi Tsai

发明人： Ming-Chung Liang ,  Shin-Yi Tsai

IPC分类号： B08B300

CPC分类号： B08B3/10

摘要： An apparatus for cleaning a semiconductor wafer is disclosed to substantially improve the efficiency of the cleaning process, and reduce the quantity of cleaning solvent used. The apparatus includes a rotating table for supporting the wafer, a rotation device to rotate the rotation table, a movable or stationary curved-slab for scrubbing the surface of the wafer efficiently, a cleaning nozzle for applying a cleaning solvent or stripper on the surface of the wafer, and a resistance wall for preventing the cleaning solvent spun out from the wafer to pollute the cleaning room.

摘要翻译： 公开了一种用于清洁半导体晶片的设备，以显着提高清洁过程的效率，并减少使用的清洗溶剂的量。 该装置包括用于支撑晶片的旋转台，用于旋转转台的旋转装置，用于高效洗刷晶片表面的可移动或固定的弯曲板，用于将清洁溶剂或剥离器施加在表面上的清洁喷嘴 晶片和用于防止从晶片纺出的清洗溶剂污染清洁室的电阻壁。

公开(公告)号：US09252060B2

公开(公告)日：2016-02-02

申请号：US13436952

申请日：2012-04-01

申请人： Chi-Ming Tsai ,  Liang-Guang Chen ,  Han-Hsin Kuo ,  Fu-Ming Huang ,  Hao-Jen Liao ,  Ming-Chung Liang

发明人： Chi-Ming Tsai ,  Liang-Guang Chen ,  Han-Hsin Kuo ,  Fu-Ming Huang ,  Hao-Jen Liao ,  Ming-Chung Liang

IPC分类号： H01L23/58 ,  H01L21/66 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L22/12 ,  H01L21/7684 ,  H01L22/30 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括衬底和布置在衬底上的互连结构。 互连结构包括多个互连层。 互连层中的一个包含：多个金属通孔插槽和设置在多个金属通孔上的体金属部件。 本公开还提供了一种方法。 该方法包括提供晶片，并在晶片上形成第一层。 该方法包括在第一层上形成互连结构。 形成互连结构包括在第一层上形成第二互连层，以及在第二互连层上形成第三互连层。 第二互连层形成为包含多个金属通孔槽和形成在多个金属通孔上的体金属部件。 第三互连层包含一个或多个金属沟槽。

公开(公告)号：US20110108994A1

公开(公告)日：2011-05-12

申请号：US12841321

申请日：2010-07-22

申请人： Ming-Chung LIANG ,  Chii-Ping CHEN

发明人： Ming-Chung LIANG ,  Chii-Ping CHEN

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76802 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/7684 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer.

摘要翻译： 一种用于形成集成电路的方法包括在晶体管的栅极上形成第一介电层。 在第一介电层上形成蚀刻停止层。 通过第一介电层和蚀刻停止层形成开口，暴露晶体管的源极/漏极（S / D）区域。 在开口中形成金属层，与晶体管的S / D区接触。 金属层具有至少部分地基本上与蚀刻停止层的第一顶表面平齐的表面。 形成镶嵌结构并与金属层耦合。

公开(公告)号：US07361604B2

公开(公告)日：2008-04-22

申请号：US10465852

申请日：2003-06-20

申请人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

发明人： Henry Wei-Ming Chung ,  Shin-Yi Tsai ,  Ming-Chung Liang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： G03F7/405 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338

摘要： A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.

摘要翻译： 一种半导体制造方法，包括在衬底上沉积第一层，在所述第一层上提供硬掩模层，图案化和限定所述硬掩模层以形成至少两个硬掩模结构，其中每个硬掩模结构包括至少一个基本垂直的侧壁和 一个基本上水平的顶部，并且其中所述硬掩模结构由第一空间分开，在所述至少两个硬掩模结构和所述第一层上沉积光敏材料，其中一定量的光敏材料沉积在 硬掩模结构基本上大于沉积在硬掩模结构的至少一个侧壁上的不敏感光材料的量，其中在其侧壁上具有光不敏感层的硬掩模结构被第二空间隔开，并且其中 第一空间大于第二空间。

公开(公告)号：US20060197180A1

公开(公告)日：2006-09-07

申请号：US11307221

申请日：2006-01-27

申请人： Erh-Kun Lai ,  Ming-Chung Liang

发明人： Erh-Kun Lai ,  Ming-Chung Liang

IPC分类号： H01L29/00

CPC分类号： H01L27/1021 ,  H01L21/8221 ,  H01L23/5252 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form a first stack circuit. Thereafter, a second stack layer is formed over the first stack circuit. The second stack layer includes, from the first stack circuit upwards, a p-type polysilicon layer, a conductive layer, an anti-fuse and another p-type polysilicon. The second stack layer is patterned to form a second stack circuit that crosses over the first stack circuit perpendicularly. The aforementioned steps are repeated to form more stack circuits above the substrate and hence produce a three-dimensional structure.

摘要翻译： 提供三维记忆结构及其制造方法。 第一堆叠层形成在衬底上。 第一堆叠层从衬底向上包括n型多晶硅层，导电层，反熔丝和另一n型多晶硅层。 图案化第一堆叠层以形成第一堆叠电路。 此后，在第一堆叠电路上形成第二堆叠层。 第二堆叠层从第一堆叠电路向上包括p型多晶硅层，导电层，反熔丝和另一p型多晶硅。 图案化第二堆叠层以形成垂直于第一堆叠电路的第二堆叠电路。 重复上述步骤以在衬底上形成更多的堆叠电路，并因此产生三维结构。