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    METHOD OF FORMING A GATE DIELECTRIC BY IN-SITU PLASMA
    4.
    发明申请
    METHOD OF FORMING A GATE DIELECTRIC BY IN-SITU PLASMA 有权
    通过现场等离子体形成栅极电介质的方法

    公开(公告)号：US20100081290A1

    公开(公告)日：2010-04-01

    申请号：US12241139

    申请日：2008-09-30

    Applicant: Tien Ying Luo ,  Olubunmi O. Adetutu

    Inventor： Tien Ying Luo ,  Olubunmi O. Adetutu

    IPC: H01L21/285

    CPC classification number: H01L21/31645 ,  C23C16/40 ,  C23C16/402 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45536 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/31641 ,  H01L29/517

    Abstract: A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.

    Abstract translation: 一种形成栅极电介质层的方法包括：使用第一等离子体在半导体衬底上形成第一电介质层，执行第一介电层的第一原位等离子体氮化，形成第一氮化电介质层，形成第二电介质层 使用第二等离子体的第一电介质层，执行第二介电层的第二原位等离子体氮化以形成第二氮化介电层; 以及对所述第一氮化介电层和所述第二氮化介电层进行退火，其中所述栅介质层包括所述第一氮化介电层和所述第二氮化介电层。 在其他实施例中，重复使用等离子体形成电介质层并执行原位等离子体氮化的步骤，以形成多于两个的氮化电介质层并用作栅极电介质层。

    Method of forming a gate dielectric by in-situ plasma
    5.
    发明授权
    Method of forming a gate dielectric by in-situ plasma 有权
    通过原位等离子体形成栅极电介质的方法

    公开(公告)号：US07981808B2

    公开(公告)日：2011-07-19

    申请号：US12241139

    申请日：2008-09-30

    Applicant: Tien Ying Luo ,  Olubunmi O. Adetutu

    Inventor： Tien Ying Luo ,  Olubunmi O. Adetutu

    IPC: H01L21/3205 ,  H01L21/31 ,  H01L21/336

    CPC classification number: H01L21/31645 ,  C23C16/40 ,  C23C16/402 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45536 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/31641 ,  H01L29/517

    Abstract: A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.

    Abstract translation: 一种形成栅极电介质层的方法包括：使用第一等离子体在半导体衬底上形成第一电介质层，执行第一介电层的第一原位等离子体氮化，形成第一氮化电介质层，形成第二电介质层 使用第二等离子体的第一电介质层，执行第二介电层的第二原位等离子体氮化以形成第二氮化介电层; 以及对所述第一氮化介电层和所述第二氮化介电层进行退火，其中所述栅介质层包括所述第一氮化介电层和所述第二氮化介电层。 在其他实施例中，重复使用等离子体形成电介质层并执行原位等离子体氮化的步骤，以形成多于两个的氮化电介质层并用作栅极电介质层。

    Method for forming a deposited oxide layer
    8.
    发明授权
    Method for forming a deposited oxide layer 有权
    形成沉积氧化物层的方法

    公开(公告)号：US07767588B2

    公开(公告)日：2010-08-03

    申请号：US11364128

    申请日：2006-02-28

    Applicant: Tien Ying Luo ,  Rajesh A. Rao

    Inventor： Tien Ying Luo ,  Rajesh A. Rao

    IPC: H01L21/31 ,  H01L21/461

    CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/31612 ,  H01L29/42332 ,  H01L29/7883 ,  H01L29/7885

    Abstract: An insulating layer formed by deposition is annealed in the presence of radical oxygen to reduce bond defects. A substrate is provided. An oxide layer is deposited overlying the substrate. The oxide layer has a plurality of bond defects. The oxide layer is annealed in the presence of radical oxygen to modify a substantial portion of the plurality of bond defects by using oxygen atoms. The anneal, in one form, is an in-situ steam generation (ISSG) anneal. In one form, the insulating layer overlies a layer of charge storage material, such as nanoclusters, that form a gate structure of a semiconductor storage device. The ISSG anneal repairs bond defects by oxidizing defective silicon bonds in the oxide layer when the oxide layer is silicon dioxide.

    Abstract translation: 通过沉积形成的绝缘层在自由基氧的存在下退火以减少键合缺陷。 提供基板。 沉积在衬底上的氧化物层。 氧化物层具有多个键合缺陷。 氧化层在自由基氧的存在下进行退火，通过使用氧原子来修饰多个键缺陷的大部分。 一种形式的退火是原位蒸汽发生（ISSG）退火。 在一种形式中，绝缘层覆盖形成半导体存储装置的栅极结构的诸如纳米团簇的电荷存储材料层。 当氧化物层是二氧化硅时，ISSG退火通过氧化氧化物层中的有缺陷的硅键来修复接合缺陷。

    Multilayer silicon nitride deposition for a semiconductor device
    9.
    发明申请
    Multilayer silicon nitride deposition for a semiconductor device 审中-公开
    用于半导体器件的多层氮化硅沉积

    公开(公告)号：US20080173908A1

    公开(公告)日：2008-07-24

    申请号：US11655461

    申请日：2007-01-19

    Applicant: Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    Inventor： Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    IPC: H01L29/78 ,  H01L21/3105 ,  H01L21/8238

    CPC classification number: H01L21/02348 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (131) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (133) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

    Abstract translation: 提供了制造半导体器件的方法，其包括（a）提供配备有栅极和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（131），所述第一应力源材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（133），所述第二应力源材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。

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