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    SILICON CARBIDE SEMICONDUCTOR DEVICE COMPRISING SILICON CARBIDE LAYER AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    SILICON CARBIDE SEMICONDUCTOR DEVICE COMPRISING SILICON CARBIDE LAYER AND METHOD OF MANUFACTURING THE SAME 有权
    含有碳化硅层的硅碳化硅半导体器件及其制造方法

    公开(公告)号：US20090250705A1

    公开(公告)日：2009-10-08

    申请号：US12267040

    申请日：2008-11-07

    申请人： Tomokatsu WATANABE ,  Sunao Aya ,  Naruhisa Miura ,  Keiko Sakai ,  Shohei Yoshida ,  Toshikazu Tanioka ,  Yukiyasu Nakao ,  Yoichiro Tarui ,  Masayuki Imaizumi

    发明人： Tomokatsu WATANABE ,  Sunao Aya ,  Naruhisa Miura ,  Keiko Sakai ,  Shohei Yoshida ,  Toshikazu Tanioka ,  Yukiyasu Nakao ,  Yoichiro Tarui ,  Masayuki Imaizumi

    IPC分类号： H01L29/24 ,  H01L21/34

    CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828

    摘要： A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C. becomes lower than that in a case where the p++ region is formed by ion implantation at a temperature over 300° C. Further, this can avoid any process failure.

    摘要翻译： 碳化硅半导体器件的p基极欧姆接触由通过高浓度离子注入形成的p ++层和金属电极组成。 由于在室温下进行的高浓度离子注入使p ++层的晶体显着降低，导致处理失败，所以使用在高温下注入的方法。 在器件的开关损耗等方面，期望p基极欧姆接触的电阻率应该更低。 在众所周知的技术中，在离子注入温度，欧姆接触电阻率和工艺故障之间的详细关系中没有提及。 然后，在离子注入步骤中，碳化硅晶片的温度保持在175℃至300℃的范围内，更优选在175℃至200℃的范围内。 在175℃〜300℃的温度范围内通过离子注入形成的p ++区域的p基极欧姆接触变得低于在超过300°的温度下通过离子注入形成p ++区域的情况下的p基极欧姆接触 此外，这可以避免任何过程失败。

    POWER SEMICONDUCTOR DEVICE
    8.
    发明申请
    POWER SEMICONDUCTOR DEVICE 审中-公开
    功率半导体器件

    公开(公告)号：US20120074508A1

    公开(公告)日：2012-03-29

    申请号：US13309305

    申请日：2011-12-01

    申请人： Kenichi OHTSUKA ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Tatsuo Oomori

    发明人： Kenichi OHTSUKA ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Tatsuo Oomori

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/66068 ,  H01L29/7828

    摘要： A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.

    摘要翻译： 功率半导体器件在其高温操作期间不容易引起用于互连的金属材料与连接到半导体区域的电极等之间的反应，并且在其高温操作期间不易于变形。 功率半导体器件可以是在形成在半导体区域上的源电极上形成含有选自Pt，Ti，Mo，W和Ta中的至少一种的第一金属层的SiC功率器件等， 例如源区域等。 在第一金属层上形成含有选自Mo，W和Cu中的至少一种的第二金属层。 在第二金属层上形成含有选自Pt，Mo和W中的至少一种的第三金属层。

    Power semiconductor device
    10.
    发明授权
    Power semiconductor device 有权
    功率半导体器件

    公开(公告)号：US08093598B2

    公开(公告)日：2012-01-10

    申请号：US12162998

    申请日：2007-03-19

    申请人： Kenichi Ohtsuka ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Tatsuo Oomori

    发明人： Kenichi Ohtsuka ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Tatsuo Oomori

    IPC分类号： H01L31/0312

    CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/66068 ,  H01L29/7828

    摘要： A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.

    摘要翻译： 功率半导体器件在其高温操作期间不容易引起用于互连的金属材料与连接到半导体区域的电极等之间的反应，并且在其高温操作期间不易于变形。 功率半导体器件可以是在形成在半导体区域上的源电极上形成含有选自Pt，Ti，Mo，W和Ta中的至少一种的第一金属层的SiC功率器件等， 例如源区域等。 在第一金属层上形成含有选自Mo，W和Cu中的至少一种的第二金属层。 在第二金属层上形成含有选自Pt，Mo和W中的至少一种的第三金属层。