公开(公告)号：US08145889B2

公开(公告)日：2012-03-27

申请号：US12912836

申请日：2010-10-27

Applicant: Osamu Nishii

Inventor： Osamu Nishii

IPC: G06F9/00

CPC classification number: G06F9/322 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3806

Abstract: A data processor or a data processing system used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. A multiple with which the displacement is multiplied can be changed in accordance with the mode.

Abstract translation: 在兼容模式下使用的数据处理器或数据处理系统，其中指定逻辑地址空间的地址的位数在通过分支指令的位移的扩展引用分支地址表时变化。 在生成第一分支指令的分支地址时，数据处理器或数据处理系统根据指定逻辑地址空间的地址的位数来优化与该位移相乘的倍数，将扩展地址 信息到寄存器的值，并且是指通过添加获得的具有地址信息的分支地址表。 所引用的信息用作分支地址。 可以根据该模式来改变与该位移相乘的倍数。

公开(公告)号：US07836286B2

公开(公告)日：2010-11-16

申请号：US12013468

申请日：2008-01-13

Applicant: Osamu Nishii

Inventor： Osamu Nishii

IPC: G06F9/44

CPC classification number: G06F9/322 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3806

Abstract: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.

Abstract translation: 本发明提供一种数据处理器或数据处理系统，其可以在兼容模式中使用，其中指定逻辑地址空间的地址的位数在通过扩展a的扩展引用分支地址表时变化 分支指令。 在生成第一分支指令的分支地址时，数据处理器或数据处理系统根据指定逻辑地址空间的地址的位数来优化与该位移相乘的倍数，将扩展地址 信息到寄存器的值，并且是指通过添加获得的具有地址信息的分支地址表。 所引用的信息用作分支地址。 为了适应于使用指定逻辑地址空间的地址的不同位数的兼容模式，根据该模式来改变与该位移相乘的倍数就足够了。

公开(公告)号：USRE41589E1

公开(公告)日：2010-08-24

申请号：US10290367

申请日：2002-11-08

Applicant: Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

Inventor： Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

IPC: G06F12/06

CPC classification number: G06F12/0215 ,  G06F13/1631

Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

Abstract translation: 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。

公开(公告)号：US20100005324A1

公开(公告)日：2010-01-07

申请号：US12346268

申请日：2008-12-30

Applicant: Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

Inventor： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC: G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Abstract translation: 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US20080201562A1

公开(公告)日：2008-08-21

申请号：US12013468

申请日：2008-01-13

Applicant: Osamu NISHII

Inventor： Osamu NISHII

IPC: G06F9/30

CPC classification number: G06F9/322 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3806

Abstract: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.

Abstract translation: 本发明提供一种数据处理器或数据处理系统，其可以在兼容模式中使用，其中指定逻辑地址空间的地址的位数在通过扩展a的扩展引用分支地址表时变化 分支指令。 在生成第一分支指令的分支地址时，数据处理器或数据处理系统根据指定逻辑地址空间的地址的位数来优化与该位移相乘的倍数，将扩展地址 信息到寄存器的值，并且是指通过添加获得的具有地址信息的分支地址表。 所引用的信息用作分支地址。 为了适应于使用指定逻辑地址空间的地址的不同位数的兼容模式，根据该模式来改变与该位移相乘的倍数就足够了。

公开(公告)号：US07143230B2

公开(公告)日：2006-11-28

申请号：US10752569

申请日：2004-01-08

Applicant: Kunio Uchiyama ,  Osamu Nishii

Inventor： Kunio Uchiyama ,  Osamu Nishii

IPC: G06F12/00

CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

公开(公告)号：US06532528B1

公开(公告)日：2003-03-11

申请号：US09563753

申请日：2000-05-01

Applicant: Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

Inventor： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

IPC: G06F1210

CPC classification number: G06F12/1027 ,  G06F2212/652

Abstract: A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

Abstract translation: 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

公开(公告)号：US5375215A

公开(公告)日：1994-12-20

申请号：US784546

申请日：1991-10-29

Applicant: Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

Inventor： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

IPC: G06F15/16 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/36 ,  G06F9/40

CPC classification number: G06F13/1642 ,  G06F13/1605

Abstract: A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access request need not wait for a previous access request to be finished. Accordingly, the throughput of the system can be improved greatly.

Abstract translation: 本发明的多处理器系统具有地址总线，数据总线，第一和第二处理器，四个访问队列和被划分为四个存储体的共享存储器。 四个访问队列由用于缓冲通过地址总线发送的多个访问请求地址的先进先出存储器构成。 即使连续访问请求被寻址到共享存储器的一个存储体，后续访问请求也不需要等待先前访问请求完成。 因此，可以大大提高系统的吞吐量。

公开(公告)号：US20110314213A1

公开(公告)日：2011-12-22

申请号：US13008189

申请日：2011-01-18

Applicant: Kunio UCHIYAMA ,  Osamu Nishii

Inventor： Kunio UCHIYAMA ,  Osamu Nishii

IPC: G06F12/00

CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

Abstract: A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.

Abstract translation: 一种处理器系统，包括：具有处理器核心和控制器核心的处理器; 以及多个同步存储器芯片，其中所述处理器和所述多个同步存储器芯片经由外部总线连接; 其中所述处理器核心和所述控制器核心经由内部总线连接; 其中所述多个同步存储器芯片根据时钟信号被操作; 其中所述控制器核心包括通过来自所述处理器核心的地址信号选择的模式寄存器，并且通过来自所述处理器核心的数据信号写入信息以选择所述多个同步存储器芯片的操作模式;以及控制单元， 基于写在模式寄存器中的信息，向多个同步存储器芯片操作模式，其中控制器核心基于写入模式寄存器中的信息或从处理器核心到多个存储器芯片的访问地址信号输出模式设置信号 选择性地通过外部总线的同步存储器芯片; 并且其中所述时钟信号被共同地提供给所述多个同步存储器芯片。

公开(公告)号：US20110208983A1

公开(公告)日：2011-08-25

申请号：US13101678

申请日：2011-05-05

Applicant: Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

Inventor： Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

IPC: G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Abstract translation: 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。