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公开(公告)号：US08788860B2
公开(公告)日：2014-07-22
申请号：US13600791
申请日：2012-08-31
CPC分类号： G05D23/19 , G06F1/32 , H01L23/34 , H01L23/38 , H01L2924/0002 , H01L2924/00
摘要： A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control.
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公开(公告)号：US20130283277A1
公开(公告)日：2013-10-24
申请号：US13453904
申请日：2012-04-23
IPC分类号： G06F9/46
CPC分类号： G06F9/5094 , G06F1/329 , Y02D10/22 , Y02D10/24
摘要： A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.
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公开(公告)号：US07865751B2
公开(公告)日：2011-01-04
申请号：US11764412
申请日：2007-06-18
CPC分类号： G05D23/19 , G06F1/32 , H01L23/34 , H01L23/38 , H01L2924/0002 , H01L2924/00
摘要： A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control.
摘要翻译： 具有多个核的装置执行一种算法来控制采用珀尔帖效应的薄膜热电冷却器（TFTEC），以从多核处理器的各种核心去除热量。 这些算法可以组合线程迁移（TM）和动态电压/频率缩放（DVFS）来提供动态热管理（DTM）和TFTEC控制。
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公开(公告)号：US20090150649A1
公开(公告)日：2009-06-11
申请号：US11953444
申请日：2007-12-10
IPC分类号： G06F9/30
CPC分类号： G11C8/04 , G06F9/30112 , G06F9/3012 , G06F9/30141 , G06F9/384
摘要： An apparatus for storing X-bit digitized data, the register file comprising: a plurality of registers each register configured for storing X bits, wherein each register is partitioned into Y sub-registers such that each sub-register stores at least X/Y bits, and wherein at least one extra X/Y-bit sub-register is incorporated in each register to provide redundancy in the number of sub-registers for a total of at least Y+1 sub-registers per register, so that if a first sub-register in a first register includes faulty bits, data destined for storage in the first sub-register is stored in a second sub-register, in the first register, that does not include faulty bits.
摘要翻译： 一种用于存储X位数字化数据的装置，所述寄存器文件包括：多个寄存器，每个寄存器被配置用于存储X位，其中每个寄存器被划分为Y个子寄存器，使得每个子寄存器至少存储X / Y位 ，并且其中在每个寄存器中并入至少一个额外的X / Y位子寄存器，以为每个寄存器总共至少Y + 1个子寄存器提供子寄存器数量的冗余，使得如果第一 第一寄存器中的子寄存器包括有故障位，第一子寄存器中存储的数据存储在第一寄存器中，不包括错误位。
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公开(公告)号：US08291168B2
公开(公告)日：2012-10-16
申请号：US13342016
申请日：2011-12-31
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/16
CPC分类号： G06F12/0895 , G06F1/3203 , G06F1/3275 , G06F1/3296 , G06F12/0864 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
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公开(公告)号：US08209989B2
公开(公告)日：2012-07-03
申请号：US11694788
申请日：2007-03-30
IPC分类号： F25B21/02
CPC分类号： F25B21/02 , F25B2321/021 , F25D2700/16 , H01L23/34 , H01L23/38 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is cooled by microarchitecture controlled Peltier effect cooling. In one embodiment, a temperature sensor thermally coupled to at least a portion of the integrated circuit of a die is adapted to provide an output as a function of the temperature of an integrated circuit portion. Operation of a thermoelectric cooler thermally coupled to the integrated circuit portion is controlled as a function of the sensor output, wherein a controller of the integrated circuit controls the thermal electric cooler. Other embodiments are described and claimed.
摘要翻译： 集成电路通过微架构控制的Peltier效应冷却来冷却。 在一个实施例中，热耦合到管芯的集成电路的至少一部分的温度传感器适于提供作为集成电路部分的温度的函数的输出。 热耦合到集成电路部分的热电冷却器的操作作为传感器输出的函数被控制，其中集成电路的控制器控制热电冷却器。 描述和要求保护其他实施例。
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7.发明申请THREAD MIGRATION TO IMPROVE POWER EFFICIENCY IN A PARALLEL PROCESSING ENVIRONMENT 有权螺旋式移动以提高平行处理环境中的功率效率公开(公告)号：US20090172424A1
公开(公告)日：2009-07-02
申请号：US11968060
申请日：2007-12-31
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/4893 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.
摘要翻译： 一种选择性地移动由多个处理核并行执行的多个线程中的一个或多个的方法和系统。 在一个实施例中，可以将线程从执行多个处理核心中的一个移动到在多个处理核心中的另一个处理核心中执行，基于与多个线程相关联的性能特性来移动线程。 在本发明的另一实施例中，可以改变多个处理核心的功率状态，以提高与执行多个线程相关联的功率效率。
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公开(公告)号：US20080310099A1
公开(公告)日：2008-12-18
申请号：US11764412
申请日：2007-06-18
IPC分类号： H05K7/20
CPC分类号： G05D23/19 , G06F1/32 , H01L23/34 , H01L23/38 , H01L2924/0002 , H01L2924/00
摘要： A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control.
摘要翻译： 具有多个核的装置执行一种算法来控制采用珀尔帖效应的薄膜热电冷却器（TFTEC），以从多核处理器的各种核心去除热量。 这些算法可以组合线程迁移（TM）和动态电压/频率缩放（DVFS）来提供动态热管理（DTM）和TFTEC控制。
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公开(公告)号：US09678878B2
公开(公告)日：2017-06-13
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08 , G06F12/126 , G06F12/0864 , G06F12/0804 , G06F1/32
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
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公开(公告)号：US20140108733A1
公开(公告)日：2014-04-17
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译： 描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。 在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。 还描述和要求保护其他实施例。
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