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28 条记录 (耗时 0.02 秒)

    Delay locked loop with frequency control
    3.
    发明授权
    Delay locked loop with frequency control 有权
    延时锁定环路带频率控制

    公开(公告)号：US07319728B2

    公开(公告)日：2008-01-15

    申请号：US10147146

    申请日：2002-05-16

    申请人： Debra M. Bell ,  Paul A. Silvestri

    发明人： Debra M. Bell ,  Paul A. Silvestri

    IPC分类号： H04L7/04 ,  H04L7/00 ,  H03L7/06

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/0814

    摘要： A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay and the cycle time of the signal exiting the delay line.

    摘要翻译： 延迟锁定环包括用于延迟从外部信号产生的输入信号的延迟线。 延迟控制器控制延迟线，以保持外部和内部信号同步。 延迟锁定环路还包括用于控制进入延迟的信号的周期时间和离开延迟线的信号的周期时间的周期控制电路。

    Method and apparatus for latency specific duty cycle correction
    4.
    发明授权
    Method and apparatus for latency specific duty cycle correction 有权
    用于延迟特定占空比校正的方法和装置

    公开(公告)号：US06768697B2

    公开(公告)日：2004-07-27

    申请号：US10230546

    申请日：2002-08-29

    申请人： Nick N. Labrum ,  Paul A. Silvestri

    发明人： Nick N. Labrum ,  Paul A. Silvestri

    IPC分类号： G11C800

    CPC分类号： H03K5/1565 ,  G11C7/22 ,  G11C11/4076

    摘要： The illustrated embodiments relate to a control circuit that uses a latency signal to generate an output signal. The latency is used to create a control signal that is dependent on the latency signal. The control signal is used to select from among multiple input sources. The selected input source is used to create an output signal.

    摘要翻译： 所示实施例涉及使用等待时间信号来产生输出信号的控制电路。 延迟用于创建取决于延迟信号的控制信号。 控制信号用于从多个输入源中进行选择。 选择的输入源用于创建输出信号。

    Tunable delay circuit
    7.
    发明授权
    Tunable delay circuit 有权
    可调延时电路

    公开(公告)号：US07142032B2

    公开(公告)日：2006-11-28

    申请号：US11003098

    申请日：2004-12-03

    申请人： Paul A. Silvestri

    发明人： Paul A. Silvestri

    IPC分类号： H03H11/26

    CPC分类号： H03L7/0812 ,  H03H11/265 ,  H03K5/133 ,  H03K2005/0013 ,  H03K2005/00136 ,  H03K2005/00143

    摘要： A delay locked loop includes a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal, and a controller responsive to a timing relationship between the feedback signal and the input signal for adjusting a timing of the output signal. The feedback path includes an adjustable delay circuit for adjusting a timing of the feedback signal.

    摘要翻译： 延迟锁定环包括用于接收输入信号以提供输出信号的前向路径，用于基于输出信号提供反馈信号的反馈路径，以及响应于反馈信号和输入信号之间的定时关系的控制器， 调整输出信号的定时。 反馈路径包括用于调整反馈信号定时的可调延迟电路。

    Alignment of memory read data and clocking
    8.
    发明授权
    Alignment of memory read data and clocking 失效
    存储器读取数据和时钟的对齐

    公开(公告)号：US07408822B2

    公开(公告)日：2008-08-05

    申请号：US11655796

    申请日：2007-01-18

    申请人： Paul A Silvestri

    发明人： Paul A Silvestri

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.

    摘要翻译： 当存储器以非常高的时钟频率操作时，电路和方法用于将从存储器读取的数据与输出时钟信号进行对准。 为了在需要时对准数据和时钟信号，在读取操作期间，延迟被添加到输出时钟信号。 这种对齐允许在否则违反时满足各种定时规范，从而提高系统中的数据完整性。

    Alignment of memory read data and clocking
    9.
    发明授权
    Alignment of memory read data and clocking 有权
    存储器读取数据和时钟的对齐

    公开(公告)号：US07184329B2

    公开(公告)日：2007-02-27

    申请号：US10888195

    申请日：2004-07-08

    申请人： Paul A Silvestri

    发明人： Paul A Silvestri

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.

    摘要翻译： 当存储器以非常高的时钟频率操作时，电路和方法用于将从存储器读取的数据与输出时钟信号进行对准。 为了在需要时对准数据和时钟信号，在读取操作期间，延迟被添加到输出时钟信号。 这种对齐允许在否则违反时满足各种定时规范，从而提高系统中的数据完整性。

    Power supply voltage detection circuitry and methods for use of the same
    10.
    发明授权
    Power supply voltage detection circuitry and methods for use of the same 有权
    电源电压检测电路及其使用方法

    公开(公告)号：US07148742B2

    公开(公告)日：2006-12-12

    申请号：US10886771

    申请日：2004-07-07

    申请人： Dong Pan ,  Feng (Dan) Lin ,  Paul A Silvestri

    发明人： Dong Pan ,  Feng (Dan) Lin ,  Paul A Silvestri

    IPC分类号： G05F1/10

    CPC分类号： G11C5/147

    摘要： Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may be accomplished with the use of bandgap reference circuitry that provides a stable bandgap reference voltage when operating in its stable operating region. The bandgap circuitry operates in conjunction with startup circuitry, which enables the bandgap circuitry to operate in its non-stable operating region. When in the non-stable region, the bandgap circuitry provides a source voltage as the reference voltage until the source voltage begins to approach the bandgap voltage, at which point the bandgap circuitry provides the stable bandgap reference voltage as the reference voltage.

    摘要翻译： 提供了提供基本上恒定的跳变点的功率检测电路。 电路不受温度和过程变化的影响，从而防止使用电路（例如，存储器）的过早或延迟启用。 此外，在慢速和快速上电和掉电条件期间，跳变点保持恒定。 这可以通过使用带隙​​参考电路来实现，该带隙参考电路在其稳定工作区域中操作时提供稳定的带隙参考电压。 带隙电路与启动电路一起工作，这使得带隙电路能够在其非稳定工作区域中工作。 当在非稳定区域中，带隙电路提供源电压作为参考电压，直到源电压开始接近带隙电压，此时带隙电路提供稳定的带隙基准电压作为参考电压。