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    Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters
    3.
    发明授权
    Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters 有权
    将目的地逻辑寄存器映射到存储移动指令的立即或重命名的源寄存器的物理寄存器，并使用映射计数器

    公开(公告)号：US06594754B1

    公开(公告)日：2003-07-15

    申请号：US09348404

    申请日：1999-07-07

    申请人： Stephan J. Jourdan ,  Gad S. Sheaffer ,  Ronny Ronen

    发明人： Stephan J. Jourdan ,  Gad S. Sheaffer ,  Ronny Ronen

    IPC分类号： G06F9315

    CPC分类号： G06F9/3857 ,  G06F9/30032 ,  G06F9/30167 ,  G06F9/384

    摘要： A computer architecture to process move instructions by allowing multiple mappings between logical registers and the same physical register. In one embodiment, a counter is associated with each physical register to indicate when the physical register is free. A register-to-register move instruction is processed by mapping the logical destination register of the move instruction to the same physical register to which the logical source register of the move instruction is mapped. An immediate-to-register move instruction is processed by mapping the logical destination register of the move instruction to a physical register storing the immediate.

    摘要翻译： 通过允许逻辑寄存器和同一物理寄存器之间的多个映射来处理移动指令的计算机体系结构。 在一个实施例中，计数器与每个物理寄存器相关联，以指示何时物理寄存器是空闲的。 通过将移动指令的逻辑目标寄存器映射到映射了移动指令的逻辑源寄存器的同一物理寄存器来处理寄存器到寄存器移动指令。 通过将移动指令的逻辑目标寄存器映射到存储立即数的物理寄存器来处理立即注册移动指令。

    Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers
    4.
    发明授权
    Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers 失效
    带有重命名设备的无序超标量微处理器，将指令从存储器映射到寄存器

    公开(公告)号：US5838941A

    公开(公告)日：1998-11-17

    申请号：US774659

    申请日：1996-12-30

    申请人： Robert C. Valentine ,  Gad S. Sheaffer ,  Ronny Ronen ,  Ilan Spillinger ,  Adi Yoaz

    发明人： Robert C. Valentine ,  Gad S. Sheaffer ,  Ronny Ronen ,  Ilan Spillinger ,  Adi Yoaz

    IPC分类号： G06F9/38 ,  G06F9/00 ,  G06F9/318

    CPC分类号： G06F9/3836 ,  G06F9/384

    摘要： An advanced register renamer comprises an associative memory having a plurality of entries, each entry storing a representation of a single operation as an expression paired with a corresponding name. The expression and the name are respectively stored in first and second fields of an entry in the memory. Both fields are available for subsequent assembly level operations to use as pattern matches. A means for converting a subsequent operation in the stream to a new operation searches for a match between an expression of the subsequent operation and the first field of a matching entry. Upon finding a match with the expression field in the table, the subsequent operation is renamed to a new operation by replacing the expression with the corresponding name field of the matching entry taken from the associative memory.

    摘要翻译： 高级寄存器重命名器包括具有多个条目的关联存储器，每个条目存储单个操作的表示作为与相应名称配对的表达式。 表达式和名称分别存储在存储器中的条目的第一和第二字段中。 两个字段都可用于后续的程序集级别操作以用作模式匹配。 用于将流中的后续操作转换为新操作的装置搜索后续操作的表达式和匹配条目的第一字段之间的匹配。 在找到与表中的表达式字段匹配时，通过将表达式替换为从关联存储器获取的匹配条目的相应名称字段，将后续操作重命名为新操作。

    Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor
    5.
    发明授权
    Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor 失效
    用于在流水线微处理器中提供重新排序的指令高速缓存的方法和装置

    公开(公告)号：US5790822A

    公开(公告)日：1998-08-04

    申请号：US621136

    申请日：1996-03-21

    申请人： Gad S. Sheaffer ,  Ronny Ronen

    发明人： Gad S. Sheaffer ,  Ronny Ronen

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3808 ,  G06F9/3802 ,  G06F9/3853

    摘要： A method and apparatus for executing instructions in a pipelined microprocessor. The method includes re-ordering the set of instructions prior to loading the instructions into an instruction cache. In one embodiment, a re-ordering unit receives the set of instructions as a trace segment made of a set of basic blocks of instructions in a logical order of execution. After being re-ordered, the instructions are presented to the reordered instruction cache in bundles. When an instruction is unavailable, possibly due to an unresolved data dependency, no operation codes (nops) are inserted into the bundle in place of an in place of an instruction, creating fixed length bundles. In a second embodiment, nops are not used. Variable length bundles are produced by using an additional bit(s) per instruction to mark the end of the bundles.

    摘要翻译： 一种用于在流水线微处理器中执行指令的方法和装置。 该方法包括在将指令加载到指令高速缓存之前重新排序指令集。 在一个实施例中，重新排序单元以逻辑执行顺序作为由一组基本指令块构成的跟踪段来接收指令集。 重新排序后，指令将以捆绑形式呈现给重新排序的指令缓存。 当指令不可用时，可能由于未解决的数据依赖关系，代替指令，不会将任何操作代码（nops）插入到bundle中，从而创建固定长度的bundle。 在第二实施例中，不使用nop。 通过使用每个指令的附加位来标记捆绑的末尾来产生可变长度束。

    DYNAMIC PINNING OF VIRTUAL PAGES SHARED BETWEEN DIFFERENT TYPE PROCESSORS OF A HETEROGENEOUS COMPUTING PLATFORM
    8.
    发明申请
    DYNAMIC PINNING OF VIRTUAL PAGES SHARED BETWEEN DIFFERENT TYPE PROCESSORS OF A HETEROGENEOUS COMPUTING PLATFORM 有权
    异步计算平台的不同类型处理器之间共享的虚拟页面动态拼接

    公开(公告)号：US20160154742A1

    公开(公告)日：2016-06-02

    申请号：US14862745

    申请日：2015-09-23

    申请人： Gad Sheaffer ,  Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann

    发明人： Gad Sheaffer ,  Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann

    IPC分类号： G06F12/10 ,  G06F13/16

    CPC分类号： G06F12/1027 ,  G06F12/0804 ,  G06F12/126 ,  G06F13/1663 ,  G06F2212/303 ,  G06F2212/657 ,  G06F2212/684

    摘要： A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing unit (GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. The device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.

    摘要翻译： 计算机系统可以支持一种或多种技术来允许由诸如图形处理单元（GPU）的非CPU设备访问的存储器页的动态固定。 非CPU可以支持虚拟到物理地址映射，并且因此可以知道可能不被固定但可被非CPU访问的存储器页。 非CPU可以向诸如与CPU相关联的设备驱动程序的运行时组件通知或发送这样的信息。 设备驱动程序可以动态地执行可由非CPU访问的这种存储器页的钉扎。 设备驱动程序甚至可以取消内存页，这可能不再被非CPU访问。 这样的方法可以允许非CPU可以不再访问的存储器页面可用于分配给其他CPU和/或非CPU。

    Translation lookaside buffer for multiple context compute engine
    9.
    发明授权
    Translation lookaside buffer for multiple context compute engine 有权
    用于多个上下文计算引擎的翻译后备缓冲区

    公开(公告)号：US09152572B2

    公开(公告)日：2015-10-06

    申请号：US13993800

    申请日：2011-12-30

    申请人： Ronny Ronen ,  Boris Ginzburg ,  Eliezer Weissmann ,  Karthikeyan Vaithianathan

    发明人： Ronny Ronen ,  Boris Ginzburg ,  Eliezer Weissmann ,  Karthikeyan Vaithianathan

    IPC分类号： G06F12/00 ,  G06F12/10 ,  G06F12/08

    CPC分类号： G06F12/1027 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

    摘要： Some implementations disclosed herein provide techniques and arrangements for an specialized logic engine that includes translation lookaside buffer to support multiple threads executing on multiple cores. The translation lookaside buffer enables the specialized logic engine to directly access a virtual address of a thread executing on one of the plurality of processing cores. For example, an acceleration compute engine may receive one or more instructions from a thread executed by a processing core. The acceleration compute engine may retrieve, based on an address space identifier associated with the one or more instructions, a physical address associated with the one or more instructions from the translation lookaside buffer to execute the one or more instructions using the physical address.

    摘要翻译： 本文公开的一些实施例提供了专用逻辑引擎的技术和布置，其包括翻译后备缓冲器以支持在多个核上执行的多个线程。 翻译后备缓冲器使得专用逻辑引擎能够直接访问在多个处理核之一上执行的线程的虚拟地址。 例如，加速计算引擎可以从由处理核心执行的线程接收一个或多个指令。 所述加速度计算引擎可以基于与所述一个或多个指令相关联的地址空间标识符，从所述翻译后备缓冲器中检索与所述一个或多个指令相关联的物理地址，以使用所述物理地址来执行所述一个或多个指令。