利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

135 条记录 (耗时 0.029 秒)

    Mailing machine transport system including a guide to reduce the impact on the weighing device caused by the trailing edge of the mailpeice
    5.
    发明授权
    Mailing machine transport system including a guide to reduce the impact on the weighing device caused by the trailing edge of the mailpeice 有权
    邮寄机运输系统包括一个引导件，以减少由邮件尾部引起的对称重装置的影响

    公开(公告)号：US08178796B2

    公开(公告)日：2012-05-15

    申请号：US12640510

    申请日：2009-12-17

    申请人： Robert J. Allen ,  Thomas M. Lyga

    发明人： Robert J. Allen ,  Thomas M. Lyga

    IPC分类号： G01G19/414 ,  G01G21/00

    CPC分类号： G01G19/002 ,  G07B17/00193 ,  G07B17/00467 ,  G07B2017/00701

    摘要： A mail processing system having a transport that reduces the amount of oscillation of the scale to allow for faster weighing of mail pieces is provided. A mailing machine includes a plurality of different modules through which mail pieces are fed by a transport system. A guide piece is provided in the transport path between the weighing module and the subsequent module, e.g., a printing module. The guide piece is structured such that forces imparted on the weighing platform of the weighing module by the trail edge of a mail piece being transported off of the weighing platform are reduced. Because of the reduction in this significant external force on the weighing platform, a faster weighing algorithm can be used on more mail pieces, thereby increasing the throughput of the mailing machine.

    摘要翻译： 提供了一种具有减少秤的振荡量以便更快地称重邮件的传送的邮件处理系统。 邮寄机包括多个不同的模块，邮件通过该模块由传送系统馈送。 在称重模块和随后的模块（例如，打印模块）之间的传送路径中提供引导件。 引导件的结构使得称重模块的称重平台上的力量被邮寄件的离开称重平台的轨迹边缘所减少。 由于称重平台上这种显着的外力减小，可以在更多的邮件上使用更快的称重算法，从而提高了邮寄机的吞吐量。

    Multi-function low profile print interface for a sheet handling device
    7.
    发明授权
    Multi-function low profile print interface for a sheet handling device 有权
    用于纸张处理设备的多功能低调打印界面

    公开(公告)号：US07845639B2

    公开(公告)日：2010-12-07

    申请号：US11731298

    申请日：2007-03-30

    申请人： Thomas M. Lyga ,  Aaron D. Smith ,  Robert J. Allen ,  James A. Fairweather ,  Neil F. Baldino

    发明人： Thomas M. Lyga ,  Aaron D. Smith ,  Robert J. Allen ,  James A. Fairweather ,  Neil F. Baldino

    IPC分类号： B65H39/10

    CPC分类号： B65H29/58 ,  B65H2402/441 ,  B65H2511/20 ,  B65H2511/51 ,  B65H2513/42 ,  B65H2513/50 ,  B65H2801/31 ,  B65H2220/02 ,  B65H2220/11 ,  B65H2220/01

    摘要： A print interface system includes a printer integrated in combination with a sheet handling system such as a mailpiece inserter. The print interface system facilitates the handling of sheet material in various operating modes, including conventional printing, duplex printing, and mailpiece creation modes. The system includes an interface module having upper and lower housing segments defining first and second feed paths. A first feed path directs sheet material to a stacking surface of the upper housing segment and a second feed path directs sheet material to a downstream module of the sheet handling device. A repositionable diverter bifurcates the path exiting the printer to direct sheet material to one of the two feed paths. Furthermore, the upper housing segment is pivotally mounted to the lower housing segment to provide internal access to one of the first and second feed paths.

    摘要翻译： 打印界面系统包括与诸如邮件插入器的片材处理系统组合的打印机。 打印接口系统便于在各种操作模式下处理片材，包括常规打印，双面打印和邮件创建模式。 该系统包括具有限定第一和第二馈送路径的上部和下部壳体段的接口模块。 第一馈送路径将片材引导到上壳体段的堆叠表面，并且第二馈送路径将片材引导到片材处理装置的下游模块。 可重新定位的分流器将离开打印机的路径分叉，将片材引导到两个进给路径中的一个。 此外，上壳体段可枢转地安装到下壳体段以提供对第一和第二馈送路径之一的内部通路。

    IC Layout Optimization to Improve Yield
    9.
    发明申请
    IC Layout Optimization to Improve Yield 有权
    IC布局优化提高产量

    公开(公告)号：US20090100386A1

    公开(公告)日：2009-04-16

    申请号：US12342353

    申请日：2008-12-23

    申请人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    发明人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

    摘要翻译： 使用制造数据和算法优化集成电路设计以提高制造产量，以识别故障概率高的区域，即关键区域。 该过程进一步改变电路设计的布局以减少临界面积，从而降低制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。