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    Fault current limiting HTS cable and method of configuring same
    1.
    发明授权
    Fault current limiting HTS cable and method of configuring same 有权
    故障电流限制HTS电缆及其配置方法

    公开(公告)号：US08886267B2

    公开(公告)日：2014-11-11

    申请号：US12951293

    申请日：2010-11-22

    申请人： Douglas C. Folts ,  James Maguire ,  Jie Yuan ,  Alexis P. Malozemoff

    发明人： Douglas C. Folts ,  James Maguire ,  Jie Yuan ,  Alexis P. Malozemoff

    IPC分类号： H01B12/02 ,  H01B12/00 ,  H01L39/24 ,  H02H7/00

    CPC分类号： H01B12/02 ,  H01B12/16 ,  H01L39/16 ,  H02H7/001 ,  H02H9/023 ,  Y02E40/641 ,  Y02E40/647 ,  Y02E40/68 ,  Y02E40/69

    摘要： A cryogenically-cooled HTS cable is configured to be included within a utility power grid having a maximum fault current that would occur in the absence of the cryogenically-cooled HTS cable. The cryogenically-cooled HTS cable includes a continuous liquid cryogen coolant path for circulating a liquid cryogen. A continuously flexible arrangement of HTS wires has an impedance characteristic that attenuates the maximum fault current by at least 10%. The continuously flexible arrangement of HTS wires is configured to allow the cryogenically-cooled HTS cable to operate, during the occurrence of a maximum fault condition, with a maximum temperature rise within the HTS wires that is low enough to prevent the formation of gas bubbles within the liquid cryogen.

    摘要翻译： 低温冷却的HTS电缆被配置为包括在具有在没有低温冷却HTS电缆的情况下将发生的最大故障电流的公用电网中。 低温冷却HTS电缆包括用于循环液体冷冻剂的连续液体冷冻剂冷却剂路径。 HTS导线的连续灵活布置具有将最大故障电流衰减至少10％的阻抗特性。 HTS导线的连续柔性布置被配置为允许低温冷却的HTS电缆在最大故障状态发生期间在HTS导线内的最大温度上升以足够低以防止气泡形成 液体冷冻剂。

    ELECTRICITY TRANSMISSION COOLING SYSTEM
    2.
    发明申请
    ELECTRICITY TRANSMISSION COOLING SYSTEM 有权
    电力传动冷却系统

    公开(公告)号：US20130065766A1

    公开(公告)日：2013-03-14

    申请号：US13607130

    申请日：2012-09-07

    申请人： Jie Yuan ,  James Maguire

    发明人： Jie Yuan ,  James Maguire

    IPC分类号： H01B12/16 ,  F25D31/00

    CPC分类号： H01B12/16 ,  H01L39/00 ,  H01L39/02 ,  H02G15/34 ,  Y02E40/647 ,  Y02E40/648

    摘要： A cooling system includes a first section of high temperature superconducting (HTS) cable configured to receive a first flow of coolant and to permit the first flow of coolant to flow therethrough. The system may further include a second section of high temperature superconducting (HTS) cable configured to receive a second flow of coolant and to permit the second flow of coolant to flow therethrough. The system may further include a cable joint configured to couple the first section of HTS cable and the second section of HTS cable. The cable joint may be in fluid communication with at least one refrigeration module and may include at least one conduit configured to permit a third flow of coolant between said cable joint and said at least one refrigeration module through a coolant line separate from said first and second sections of HTS cable.

    摘要翻译： 冷却系统包括高温超导（HTS）电缆的第一部分，其被配置为接收第一冷却剂流并且允许第一流动的冷却剂流过其中。 该系统可以进一步包括高温超导（HTS）电缆的第二部分，其被配置为接收第二冷却剂流并且允许第二流动的冷却剂流过其中。 该系统还可以包括电缆接头，其被配置为将HTS电缆的第一部分和HTS电缆的第二部分耦合。 电缆接头可以与至少一个制冷模块流体连通，并且可以包括至少一个导管，其构造成允许在所述电缆接头和所述至少一个制冷模块之间通过与所述第一和第二制冷模块分离的冷却剂管线进行第三流动的冷却剂流 HTS电缆部分。

    Quantum-limited highly linear CMOS detector for computer tomography
    4.
    发明申请
    Quantum-limited highly linear CMOS detector for computer tomography 有权
    量子限制高线性CMOS检测器用于计算机断层扫描

    公开(公告)号：US20110291019A1

    公开(公告)日：2011-12-01

    申请号：US13115681

    申请日：2011-05-25

    申请人： Jie Yuan ,  Bing Liu

    发明人： Jie Yuan ,  Bing Liu

    IPC分类号： G01T1/24

    CPC分类号： G01T1/249 ,  G01T1/247

    摘要： The invention provides a CMOS CT detector design with high linearity, quantum-limited noise, good scalability, high fill factor with a single CMOS chip utilizing synchronous partial quantization. The CMOS CT detector includes a pixel array, digital column buses, analog column buses, column processing circuits, a shift register, a control signal generation circuit, and a reference generation circuit, and implements a synchronous partial quantization scheme with reset, integration and analog readout phases. Each pixel of the pixel array further includes a photodiode; an integration capacitor; an OPAMP; a reset switch; a comparator; a 1-bit dynamic random-access-memory (DRAM) cell; a circuit block for enabling subtraction of a substantially fixed amount of charge from the integrated photocharge if the integrated photovoltage increases beyond the reference voltage; an integration node; an analog buffer; and a switch coupled between the output of the DRAM cell and the digital column bus. The inclusion of a level-shifter and a current front-end improves the linearity of the detector.

    摘要翻译： 本发明提供了具有高线性，量子限制噪声，良好的可扩展性，高填充率的CMOS CT检测器设计，其具有利用同步部分量化的单个CMOS芯片。 CMOS CT检测器包括像素阵列，数字列总线，模拟列总线，列处理电路，移位寄存器，控制信号生成电路和参考生成电路，并实现具有复位，积分和模拟的同步部分量化方案 读出阶段。 像素阵列的每个像素还包括光电二极管; 集成电容器; 一个OPAMP; 复位开关; 比较器 1位动态随机存取存储器（DRAM）单元; 电路块，用于如果集成的光电压增加超过参考电压，则能够从集成的光电荷中减去基本固定的电荷量; 集成节点; 模拟缓冲器 以及耦合在DRAM单元的输出和数字列总线之间的开关。 包括电平转换器和电流前端提高了检测器的线性度。

    Method of fabricating plasma reactor parts
    5.
    发明授权
    Method of fabricating plasma reactor parts 有权
    制造等离子体反应器部件的方法

    公开(公告)号：US07942965B2

    公开(公告)日：2011-05-17

    申请号：US11688011

    申请日：2007-03-19

    申请人： Elmira Ryabova ,  Jie Yuan ,  Jennifer Sun

    发明人： Elmira Ryabova ,  Jie Yuan ,  Jennifer Sun

    IPC分类号： C30B1/02

    CPC分类号： C30B25/00 ,  C30B29/06 ,  C30B33/02 ,  H01J37/32495 ,  H01J37/32642

    摘要： A method of fabricating silicon parts are provided herein. The method includes growing a silicon sample, machining the sample to form a part, and annealing the part by exposing the part sequentially to one or more gases. Process conditions during silicon growth and post-machining anneal are designed to provide silicon parts that are particularly suited for use in corrosive environments.

    摘要翻译： 本文提供了制造硅部件的方法。 该方法包括生长硅样品，加工样品以形成部分，以及通过将部件依次暴露于一种或多种气体来对部件进行退火。 硅生长和后加工退火过程中的工艺条件被设计成提供特别适用于腐蚀性环境的硅部件。

    Fault current limiting HTS cable and method of configuring same
    6.
    发明授权
    Fault current limiting HTS cable and method of configuring same 有权
    故障电流限制HTS电缆及其配置方法

    公开(公告)号：US07902461B2

    公开(公告)日：2011-03-08

    申请号：US11688809

    申请日：2007-03-20

    申请人： Douglas C. Folts ,  James Maguire ,  Jie Yuan ,  Alexis P. Malozemoff

    发明人： Douglas C. Folts ,  James Maguire ,  Jie Yuan ,  Alexis P. Malozemoff

    IPC分类号： H01B12/00

    CPC分类号： H01B12/02 ,  H01B12/16 ,  H01L39/16 ,  H02H7/001 ,  H02H9/023 ,  Y02E40/641 ,  Y02E40/647 ,  Y02E40/68 ,  Y02E40/69

    摘要： A cryogenically-cooled HTS cable is configured to be included within a utility power grid having a maximum fault current that would occur in the absence of the cryogenically-cooled HTS cable. The cryogenically-cooled HTS cable includes a continuous liquid cryogen coolant path for circulating a liquid cryogen. A continuously flexible arrangement of HTS wires has an impedance characteristic that attenuates the maximum fault current by at least 10%. The continuously flexible arrangement of HTS wires is configured to allow the cryogenically-cooled HTS cable to operate, during the occurrence of a maximum fault condition, with a maximum temperature rise within the HTS wires that is low enough to prevent the formation of gas bubbles within the liquid cryogen.

    摘要翻译： 低温冷却的HTS电缆被配置为包括在具有在没有低温冷却HTS电缆的情况下将发生的最大故障电流的公用电网中。 低温冷却HTS电缆包括用于循环液体冷冻剂的连续液体冷冻剂冷却剂路径。 HTS导线的连续灵活布置具有将最大故障电流衰减至少10％的阻抗特性。 HTS导线的连续柔性布置被配置为允许低温冷却的HTS电缆在最大故障状态发生期间在HTS导线内的最大温度上升以足够低以防止气泡形成 液体冷冻剂。

    COMPONENT COOLING SYSTEM
    8.
    发明申请
    COMPONENT COOLING SYSTEM 审中-公开
    组件冷却系统

    公开(公告)号：US20090241558A1

    公开(公告)日：2009-10-01

    申请号：US12059951

    申请日：2008-03-31

    申请人： Jie Yuan ,  James Maguire

    发明人： Jie Yuan ,  James Maguire

    IPC分类号： F25B19/00

    CPC分类号： F25D19/006 ,  F25B2400/01 ,  F25B2400/17 ,  H01F6/04

    摘要： A component cooling system includes a component tank configured to receive a heat-generating device. The component tank is at least partially filled with a subcooled liquid at a first pressure and at a first temperature. A cryogenic system maintains the component tank at essentially the first temperature. The cryogenic system includes a heat exchange system thermally coupled with at least a portion of the component tank. The heat exchange system is at least partially filled with a second saturated liquid at a second pressure and at essentially the first temperature. A cryostat tank is fluidly-coupled with the heat exchange system and allows for pumpless displacement of the second saturated liquid between the heat exchange system and the cryostat tank.

    摘要翻译： 部件冷却系统包括构造成接收发热装置的部件箱。 组件箱在第一压力和第一温度下至少部分地填充有过冷液体。 低温系统将组分罐保持在基本上第一温度。 低温系统包括与组件箱的至少一部分热联接的热交换系统。 热交换系统在第二压力和基本上第一温度下至少部分地被第二饱和液体填充。 低温恒温箱与热交换系统流体耦合，并允许第二饱和液体在热交换系统和低温恒温箱之间的无位移。

    Characterizing circuit performance by separating device and interconnect impact on signal delay
    9.
    发明授权
    Characterizing circuit performance by separating device and interconnect impact on signal delay 有权
    通过分离器件和互连对信号延迟的影响来表征电路性能

    公开(公告)号：US07489152B2

    公开(公告)日：2009-02-10

    申请号：US11498371

    申请日：2006-08-03

    申请人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    发明人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    摘要翻译： 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。