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    Power semiconductor device
    2.
    发明申请
    Power semiconductor device 审中-公开
    功率半导体器件

    公开(公告)号：US20060237786A1

    公开(公告)日：2006-10-26

    申请号：US11384260

    申请日：2006-03-21

    申请人： Hideaki Ninomiya ,  Masanobu Tsuchitani ,  Satoshi Teramae ,  Masakazu Yamaguchi ,  Koichi Sugiyama ,  Satoshi Urano ,  Keiko Kawamura

    发明人： Hideaki Ninomiya ,  Masanobu Tsuchitani ,  Satoshi Teramae ,  Masakazu Yamaguchi ,  Koichi Sugiyama ,  Satoshi Urano ,  Keiko Kawamura

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7397 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7393

    摘要： A power semiconductor device according to the present invention comprises: a first conductive type base layer; a second conductive type base layer selectively formed on the first conductive type base layer; an insulation layer formed in the region on the first conductive type base layer on which the second conductive type base layer is not formed; a gate insulation film formed on the inner surface of a trench formed between the second conductive type base layer and the insulation layer so as to separate them from each other and to reach the first conductive type base layer from the surface of the second conductive type base layer; a first conductive type source layer selectively formed on the surface of the second conductive type base layer in contact with the gate insulation film; a gate electrode formed in the trench and insulated from the first conductive type base layer, the second conductive type base layer, and the first conductive type source layer by the gate insulation film; a main electrode electrically connected to the first conductive type base layer and the second conductive type base layer; and a first conductive type or second conductive type floating layer formed on the bottom of the insulation layer.

    摘要翻译： 根据本发明的功率半导体器件包括：第一导电型基极层; 选择性地形成在所述第一导电型基底层上的第二导电型基底层; 形成在不形成第二导电型基底层的第一导电型基底层上的区域中的绝缘层; 形成在形成在第二导电型基极层和绝缘层之间的沟槽的内表面上以便将它们彼此分离并从第二导电类型基底的表面到达第一导电型基极的栅极绝缘膜 层; 选择性地形成在与所述栅极绝缘膜接触的所述第二导电型基底层的表面上的第一导电型源极层; 形成在所述沟槽中的栅电极，通过所述栅极绝缘膜与所述第一导电型基极层，所述第二导电型基极层和所述第一导电型源极绝缘; 电连接到第一导电型基极层和第二导电型基极层的主电极; 以及形成在绝缘层的底部上的第一导电型或第二导电型浮动层。

    Insulated gate semiconductor device
    3.
    发明申请
    Insulated gate semiconductor device 有权
    绝缘栅半导体器件

    公开(公告)号：US20050280078A1

    公开(公告)日：2005-12-22

    申请号：US11154743

    申请日：2005-06-17

    申请人： Satoshi Teramae ,  Shigeru Hasegawa ,  Hideaki Ninomiya ,  Masahiro Tanaka

    发明人： Satoshi Teramae ,  Shigeru Hasegawa ,  Hideaki Ninomiya ,  Masahiro Tanaka

    IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/739 ,  H01L29/76

    CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/41741

    摘要： An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate so as to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the device region and divided in segments by insulated trench-shaped gates so as to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, and a connection part to electrically connect the peripheral diffusion region to the emitter electrode.

    摘要翻译： 一种绝缘栅半导体器件，包括沿着半导体衬底的周边形成在循环部分中的隔离结构，以将该部分与内部器件区域隔离，位于隔离结构外部的半导体衬底的外围扩散区域，多个 在器件区域中定义并由绝缘的沟槽状栅极划分成段的单元结构，以便在其上表面上覆盖有发射极区域的基极区域，集电极区域和电连接到发射极区域的发射极电极， 所述基极区域，与所述单元结构邻接的虚设基极区域，并且被配置为其上表面保持没有发射极区域连接到所述发射极的基极区域;以及连接部分，用于将所述外围扩散区域电连接到所述发射极电极 。

    Insulated gate semiconductor device
    6.
    发明授权
    Insulated gate semiconductor device 有权
    绝缘栅半导体器件

    公开(公告)号：US07211861B2

    公开(公告)日：2007-05-01

    申请号：US11154743

    申请日：2005-06-17

    申请人： Satoshi Teramae ,  Shigeru Hasegawa ,  Hideaki Ninomiya ,  Masahiro Tanaka

    发明人： Satoshi Teramae ,  Shigeru Hasegawa ,  Hideaki Ninomiya ,  Masahiro Tanaka

    IPC分类号： H01L29/06

    CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/41741

    摘要： An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the inside device region and divided in segments by insulated trench-shaped gates to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, an inner region defined in and insulated from the dummy base region, and a connection part to electrically connect the inner region to the emitter electrode.

    摘要翻译： 一种绝缘栅半导体器件，包括沿着半导体衬底的周边形成在循环部分中的隔离结构，以将该部分与内部器件区域隔离，位于隔离结构外部的半导体衬底的外围扩散区域，多个电池单元 在内部器件区域中限定的结构，并由绝缘的沟槽形状的栅极分割成具有覆盖在其上表面的发射极区域的基极区域，集电极区域和与发射极区域和基极区域电连接的发射极电极 ，与单元结构邻接的虚拟基极区域，并且被配置为具有其上表面没有发射极区域连接到发射极电极的基极区域，限定在虚拟基极区域中并与虚拟基极区域绝缘的内部区域，以及连接部分 将内部区域电连接到发射极。