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公开(公告)号：US20070298521A1
公开(公告)日：2007-12-27
申请号：US11669759
申请日：2007-01-31
申请人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
发明人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
IPC分类号： H01L21/00
CPC分类号： H01L21/02071 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/022 , H01L21/02263 , H01L21/31683 , H01L28/55 , H01L28/65
摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.
摘要翻译： 提出了制造半导体器件的方法。 一方面，该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。 该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。 转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。 转化还包括氧化金属氢氧化物以形成非导电金属氧化物。
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公开(公告)号：US07723199B2
公开(公告)日：2010-05-25
申请号：US11669759
申请日：2007-01-31
申请人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
发明人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
IPC分类号： H01L21/02
CPC分类号： H01L21/02071 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/022 , H01L21/02263 , H01L21/31683 , H01L28/55 , H01L28/65
摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.
摘要翻译： 提出了制造半导体器件的方法。 一方面，该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。 该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。 转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。 转化还包括氧化金属氢氧化物以形成非导电金属氧化物。
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公开(公告)号：US20090194801A1
公开(公告)日：2009-08-06
申请号：US12025207
申请日：2008-02-04
申请人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
CPC分类号： H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.
摘要翻译： 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。
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公开(公告)号：US07985603B2
公开(公告)日：2011-07-26
申请号：US12025207
申请日：2008-02-04
申请人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
CPC分类号： H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.
摘要翻译： 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。
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5.发明授权公开(公告)号：US08093070B2
公开(公告)日：2012-01-10
申请号：US11706722
申请日：2007-02-15
申请人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
发明人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L21/00
CPC分类号： H01L28/75 , H01L27/11507 , H01L28/55
摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
摘要翻译： 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。
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6.发明申请公开(公告)号：US20080081380A1
公开(公告)日：2008-04-03
申请号：US11706722
申请日：2007-02-15
申请人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
发明人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L21/00
CPC分类号： H01L28/75 , H01L27/11507 , H01L28/55
摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
摘要翻译： 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。
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公开(公告)号：US07220600B2
公开(公告)日：2007-05-22
申请号：US11016400
申请日：2004-12-17
CPC分类号： H01L21/0206 , H01L21/02071 , H01L28/55 , H01L28/57 , H01L28/65 , H01L28/75
摘要： Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.
摘要翻译： 提供了用于制造铁电电容器结构的方法（100），其包括用于在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法（128）。 所述方法包括：上电极的蚀刻（140,200）部分，蚀刻（141,201）铁电材料和蚀刻（142,202）下电极以限定图案化的铁电电容器结构，以及蚀刻（143,206）a 部分下部电极扩散阻挡结构。 所述方法还包括使用第一灰化处理灰化（144,203）所述图案化的铁电电容器结构，在第一灰化处理之后执行（145,204）湿式清洁处理，以及使用所述图案化铁电电容器结构灰化（146,205） 在氧化环境中的高温下在湿式清洁工艺之后直接进行第二次灰化处理。
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8.发明授权公开(公告)号：US07935543B2
公开(公告)日：2011-05-03
申请号：US12472265
申请日：2009-05-26
IPC分类号： H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.
摘要翻译： 本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到铁电芯的居里温度附近的温度，并对衬底进行温度程序 ，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。 本发明的实施例包括在铁电体芯上方和下方扩展横截面的金属填充通孔，其增加了在冷却期间铁电芯上的热应力。
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9.发明授权Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化公开(公告)号：US07572698B2
公开(公告)日：2009-08-11
申请号：US11442810
申请日：2006-05-30
IPC分类号： H01L21/336
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译： 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。
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10.发明申请Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化公开(公告)号：US20070281422A1
公开(公告)日：2007-12-06
申请号：US11442810
申请日：2006-05-30
IPC分类号： H01L21/336
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译： 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。
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