公开(公告)号：US20070298521A1

公开(公告)日：2007-12-27

申请号：US11669759

申请日：2007-01-31

申请人： Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

发明人： Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

IPC分类号： H01L21/00

CPC分类号： H01L21/02071 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02263 ,  H01L21/31683 ,  H01L28/55 ,  H01L28/65

摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

摘要翻译： 提出了制造半导体器件的方法。 一方面，该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。 该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。 转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。 转化还包括氧化金属氢氧化物以形成非导电金属氧化物。

公开(公告)号：US07723199B2

公开(公告)日：2010-05-25

申请号：US11669759

申请日：2007-01-31

申请人： Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

发明人： Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

IPC分类号： H01L21/02

CPC分类号： H01L21/02071 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02263 ,  H01L21/31683 ,  H01L28/55 ,  H01L28/65

摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

摘要翻译： 提出了制造半导体器件的方法。 一方面，该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。 该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。 转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。 转化还包括氧化金属氢氧化物以形成非导电金属氧化物。

公开(公告)号：US20090194801A1

公开(公告)日：2009-08-06

申请号：US12025207

申请日：2008-02-04

申请人： Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

发明人： Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

IPC分类号： H01L27/00 ,  H01L21/00

CPC分类号： H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.

摘要翻译： 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。

公开(公告)号：US07985603B2

公开(公告)日：2011-07-26

申请号：US12025207

申请日：2008-02-04

申请人： Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

发明人： Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

IPC分类号： H01L21/00 ,  H01L21/02

CPC分类号： H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.

摘要翻译： 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。

公开(公告)号：US07939400B2

公开(公告)日：2011-05-10

申请号：US12235766

申请日：2008-09-23

申请人： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

发明人： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC分类号： H01L21/8238

CPC分类号： H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

摘要翻译： 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US07678713B2

公开(公告)日：2010-03-16

申请号：US11196985

申请日：2005-08-04

申请人： Ting Y. Tsui ,  Andrew McKerrow ,  Satyavolu Srinivas Papa Rao ,  Robert Kraft

发明人： Ting Y. Tsui ,  Andrew McKerrow ,  Satyavolu Srinivas Papa Rao ,  Robert Kraft

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76825

摘要： The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

摘要翻译： 本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。 提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或 弹性模量增加值。

公开(公告)号：US07442597B2

公开(公告)日：2008-10-28

申请号：US11049275

申请日：2005-02-02

申请人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

发明人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC分类号： H01L21/8238

CPC分类号： H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

摘要翻译： 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US07087518B2

公开(公告)日：2006-08-08

申请号：US10438566

申请日：2003-05-15

申请人： David Gerald Farber ,  William Wesley Dostalik ,  Robert Kraft ,  Andrew J. McKerrow ,  Kenneth Joseph Newton ,  Ting Tsui

发明人： David Gerald Farber ,  William Wesley Dostalik ,  Robert Kraft ,  Andrew J. McKerrow ,  Kenneth Joseph Newton ,  Ting Tsui

IPC分类号： H01L21/322

CPC分类号： H01L21/76829 ,  H01L21/306 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/76801

摘要： One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

公开(公告)号：US06872665B1

公开(公告)日：2005-03-29

申请号：US09599718

申请日：2000-06-22

申请人： Francis G. Celii ,  Guoqiang Xing ,  Andrew McKerrow ,  Andrew Ralston ,  Zhicheng Tang ,  Kenneth J. Newton ,  Robert Kraft ,  Jeff West

发明人： Francis G. Celii ,  Guoqiang Xing ,  Andrew McKerrow ,  Andrew Ralston ,  Zhicheng Tang ,  Kenneth J. Newton ,  Robert Kraft ,  Jeff West

IPC分类号： H01L21/768 ,  H01L21/20

CPC分类号： H01L21/76808

摘要： A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.

摘要翻译： 用于形成互连线和通孔的双镶嵌工艺流程，其中在沟槽蚀刻之前蚀刻至少部分通孔（116）。 使用低k材料如热固性有机聚合物用于ILD（106）和IMD（110）。 在至少部分通孔蚀刻之后，BARC（120）沉积在包括在通孔（116）中的结构上。 然后，对沟槽（126）进行图案化和蚀刻。 虽然在沟槽蚀刻期间去除了至少一些BARC（120）材料，但是通孔（116）的底部被保护。

公开(公告)号：US06399445B1

公开(公告)日：2002-06-04

申请号：US09212508

申请日：1998-12-15

申请人： Sunil V. Hattangady ,  Srikanth Krishnan ,  Robert Kraft

发明人： Sunil V. Hattangady ,  Srikanth Krishnan ,  Robert Kraft

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3215 ,  H01L29/513 ,  H01L29/518

摘要： A method of fabricating a semiconductor MOS device and the device wherein there is initially provided a semiconductor substrate having a gate insulator layer thereon and intimate therewith. A region of one of a nitride or oxynitride is formed at the surface region of the layer remote from the substrate having sufficient nitride to act as a barrier against the migration of dopant therethrough to the substrate. A doped polysilicon gate or a metal gate is then formed over the region of a nitride or oxynitride. The amount of nitride in the insulator layer intimate and closely adjacent to the substrate is insufficient to materially alter the characteristics of the device being fabricated. The substrate is preferably silicon, the oxide and nitride are preferably those of silicon and the dopant preferably includes boron. The step of forming a region of one of a nitride or oxynitride includes the step of injecting neutral atomic nitrogen into the surface of the gate insulator layer surface remote from the substrate. The region of one of a nitride or oxynitride is from about 1 to about 2 monolayers.

摘要翻译： 一种制造半导体MOS器件的方法及其装置，其中最初提供了一种半导体衬底，其上具有栅极绝缘体层并且具有密封性。 氮化物或氮氧化物之一的区域形成在远离具有足够氮化物的衬底的层的表面区域上，以作为防止掺杂剂向衬底迁移的阻挡层。 然后在氮化物或氮氧化物的区域上形成掺杂的多晶硅栅极或金属栅极。 绝缘体层中与衬底紧密并紧密相邻的氮化物的量不足以实质上改变正在制造的器件的特性。 衬底优选为硅，氧化物和氮化物优选为硅，掺杂剂优选包括硼。 形成氮化物或氮氧化物之一的区域的步骤包括将中性原子氮注入远离衬底的栅极绝缘体层表面的步骤。 氮化物或氧氮化物之一的区域为约1至约2个单层。