公开(公告)号：US08901644B2

公开(公告)日：2014-12-02

申请号：US13821944

申请日：2011-09-09

申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L29/775 ,  H01L29/06 ,  H01L21/28 ,  H01L29/41 ,  H01L29/423

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  H01L21/2815 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/413 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

摘要： Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

摘要翻译： 本文公开了具有垂直沟道的场效应晶体管及其制造方法。 场效应晶体管的沟道区域是形成在衬底上并垂直于衬底的圆形环形Si平台; 由多晶硅制成的源头位于Si平台的上端; 在圆环状Si平台的下端的外侧配置有排水口， 在圆环状Si平台的外侧面上设置有闸门; 并且圆形环形Si平台的内部填充有电介质材料。 与传统的具有Si平台的垂直结构MOSFET相比，根据本发明的圆环形结构场效应晶体管可以有效地抑制短沟道效应并提高器件性能。

公开(公告)号：US20130168759A1

公开(公告)日：2013-07-04

申请号：US13821944

申请日：2011-09-09

申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  H01L21/2815 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/413 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

摘要： Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

摘要翻译： 本文公开了具有垂直沟道的场效应晶体管及其制造方法。 场效应晶体管的沟道区域是形成在衬底上并垂直于衬底的圆形环形Si平台; 由多晶硅制成的源头位于Si平台的上端; 在圆环状Si平台的下端的外侧配置有排水口， 在圆环状Si平台的外侧面上设置有闸门; 并且圆形环形Si平台的内部填充有电介质材料。 与传统的具有Si平台的垂直结构MOSFET相比，根据本发明的圆环形结构场效应晶体管可以有效地抑制短沟道效应并提高器件性能。

公开(公告)号：US20120190202A1

公开(公告)日：2012-07-26

申请号：US13379752

申请日：2011-09-09

申请人： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

发明人： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

IPC分类号： H01L21/311 ,  B82Y40/00

CPC分类号： B82Y40/00

摘要： The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.

摘要翻译： 本发明公开了一种制造半导体纳米圆环的方法。 在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。 然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。 本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本 环状纳米结构。

公开(公告)号：US08722312B2

公开(公告)日：2014-05-13

申请号：US13379752

申请日：2011-09-09

申请人： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

发明人： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

IPC分类号： G03F7/20

CPC分类号： B82Y40/00

摘要： The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.

摘要翻译： 本发明公开了一种制造半导体纳米圆环的方法。 在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。 然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。 本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本 环状纳米结构。

公开(公告)号：US20120115297A1

公开(公告)日：2012-05-10

申请号：US13133643

申请日：2010-09-25

申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.

摘要翻译： 本发明公开了一种基于平面工艺自对准地制造隧道场效应晶体管（TFET）的方法，从而降低了用于制造平面TFET的光刻工艺的要求。 在该方法中，TFET的源极区域和漏极区域不直接由光刻法定义; 相反，它们由位于栅极的有源区域和两侧上并且不同于限定沟道区域的电介质膜的另一介电膜限定。 通过用蚀刻选择性地去除源极和漏极区域上的电介质膜，可以消除用于限定沟道区域，源极和漏极区域的三次光刻处理之间由于取向偏差引起的影响。 因此，可以基于该工艺自平面地制造平面TFET，从而减轻了在平面TFET的制造过程期间对光刻的对准偏差的刚性要求，这有助于制造具有稳定和可靠的平面TFET器件 特点

公开(公告)号：US08288238B2

公开(公告)日：2012-10-16

申请号：US13133643

申请日：2010-09-25

申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.

摘要翻译： 本发明公开了一种基于平面工艺自对准地制造隧道场效应晶体管（TFET）的方法，从而降低了用于制造平面TFET的光刻工艺的要求。 在该方法中，TFET的源极区域和漏极区域不直接由光刻法定义; 相反，它们由位于栅极的有源区域和两侧上并且不同于限定沟道区域的电介质膜的另一介电膜限定。 通过用蚀刻选择性地去除源极和漏极区域上的电介质膜，可以消除用于限定沟道区域，源极和漏极区域的三次光刻处理之间由于取向偏差的影响。 因此，可以基于该工艺自平面地制造平面TFET，从而减轻了在平面TFET的制造过程期间对光刻的对准偏差的刚性要求，这有助于制造具有稳定和可靠的平面TFET器件 特点

公开(公告)号：US20120238097A1

公开(公告)日：2012-09-20

申请号：US13513852

申请日：2011-09-29

申请人： Ru Huang ,  Shuangshuang Pu ,  Yujie Ai ,  Zhihua Hao ,  Runsheng Wang

发明人： Ru Huang ,  Shuangshuang Pu ,  Yujie Ai ,  Zhihua Hao ,  Runsheng Wang

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  B82Y30/00 ,  B82Y40/00 ,  H01L28/20

摘要： Disclosed herein is a method for fabricating a fine line, which belongs to a field of ultra-large-scale integrated circuit manufacturing technology. In the invention, three trimming mask processes are performed to effectively improve a profile of the line and greatly reduce the LER (line edge roughness) of the line. At the same time, the invention is combined with a sidewall process, so that a nano-scaled fine line can be successfully fabricated and precisely controlled to 20 nm. Thus, a nano-scaled line with an optimized LER can be fabricated over the substrate.

摘要翻译： 这里公开了一种属于超大规模集成电路制造技术领域的细线的制造方法。 在本发明中，执行三个修整掩模处理以有效地改善线的轮廓并大大降低线的LER（线边缘粗糙度）。 同时，本发明与侧壁工艺相结合，可以成功制作纳米级细线，精确控制为20nm。 因此，可以在衬底上制造具有优化的LER的纳米级线。