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    METHOD FOR FABRICATING SEMICONDUCTOR NANO CIRCULAR RING
    3.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR NANO CIRCULAR RING 有权
    制造半导体纳米圆环的方法

    公开(公告)号：US20120190202A1

    公开(公告)日：2012-07-26

    申请号：US13379752

    申请日：2011-09-09

    申请人： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

    发明人： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

    IPC分类号： H01L21/311 ,  B82Y40/00

    CPC分类号： B82Y40/00

    摘要： The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.

    摘要翻译： 本发明公开了一种制造半导体纳米圆环的方法。 在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。 然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。 本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本 环状纳米结构。

    Method for fabricating semiconductor nano circular ring
    4.
    发明授权
    Method for fabricating semiconductor nano circular ring 有权
    制造半导体纳米圆环的方法

    公开(公告)号：US08722312B2

    公开(公告)日：2014-05-13

    申请号：US13379752

    申请日：2011-09-09

    申请人： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

    发明人： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

    IPC分类号： G03F7/20

    CPC分类号： B82Y40/00

    摘要： The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.

    摘要翻译： 本发明公开了一种制造半导体纳米圆环的方法。 在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。 然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。 本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本 环状纳米结构。

    METHOD FOR FABRICATING ULTRA-FINE NANOWIRE
    5.
    发明申请
    METHOD FOR FABRICATING ULTRA-FINE NANOWIRE 审中-公开
    制造超细纳米线的方法

    公开(公告)号：US20130130503A1

    公开(公告)日：2013-05-23

    申请号：US13511624

    申请日：2012-02-03

    申请人： Ru Huang ,  Shuai Sun ,  Yujie Ai ,  Jiewen Fan ,  Runsheng Wang ,  Xiaoyan Xu

    发明人： Ru Huang ,  Shuai Sun ,  Yujie Ai ,  Jiewen Fan ,  Runsheng Wang ,  Xiaoyan Xu

    IPC分类号： H01L21/308 ,  B82Y40/00

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L29/0673

    摘要： Disclosed herein is a method for fabricating an ultra-fine nanowire by combining a trimming process and a mask blocking oxidation process. The ultra-thin nanowire is fabricated by a combination of performing a trimming process on a mask to reduce a width of the mask and blocking an oxidation through the mask. A diameter of the floated ultra-thin nanowire fabricated by the method is controlled to 20 nm below by a thickness of a deposited silicon oxide film, a width of the silicon oxide nanowire after trimming, and a time and a temperature for performing a wet oxidation process. Also, since a speed of the wet oxidation process is faster, the width of the nanowire obtained by a conventional photolithography is reduced faster. Moreover, when fabricating an ultra-thin nanowire by using the method, the cost is reduced and it is more feasible to be implemented.

    摘要翻译： 本文公开了通过组合修整工艺和掩模阻挡氧化工艺来制造超细纳米线的方法。 超薄纳米线通过对掩模进行修整处理以减少掩模的宽度并阻挡通过掩模的氧化的组合来制造。 通过该方法制造的漂浮的超薄纳米线的直径通过沉积的氧化硅膜的厚度，修整后的氧化硅纳米线的宽度以及进行湿氧化的时间和温度控制在20nm以下 处理。 此外，由于湿式氧化处理的速度更快，所以通过常规光刻获得的纳米线的宽度更快地降低。 此外，当通过使用该方法制造超薄纳米线时，成本降低，并且更可行。

    METHOD FOR FABRICATING A TUNNELING FIELD-EFFECT TRANSISTOR
    6.
    发明申请
    METHOD FOR FABRICATING A TUNNELING FIELD-EFFECT TRANSISTOR 有权
    制造隧道场效应晶体管的方法

    公开(公告)号：US20120115297A1

    公开(公告)日：2012-05-10

    申请号：US13133643

    申请日：2010-09-25

    申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

    发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7391 ,  H01L29/66356

    摘要： The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.

    摘要翻译： 本发明公开了一种基于平面工艺自对准地制造隧道场效应晶体管（TFET）的方法，从而降低了用于制造平面TFET的光刻工艺的要求。 在该方法中，TFET的源极区域和漏极区域不直接由光刻法定义; 相反，它们由位于栅极的有源区域和两侧上并且不同于限定沟道区域的电介质膜的另一介电膜限定。 通过用蚀刻选择性地去除源极和漏极区域上的电介质膜，可以消除用于限定沟道区域，源极和漏极区域的三次光刻处理之间由于取向偏差引起的影响。 因此，可以基于该工艺自平面地制造平面TFET，从而减轻了在平面TFET的制造过程期间对光刻的对准偏差的刚性要求，这有助于制造具有稳定和可靠的平面TFET器件 特点

    Method for fabricating a tunneling field-effect transistor
    7.
    发明授权
    Method for fabricating a tunneling field-effect transistor 有权
    隧道场效应晶体管的制造方法

    公开(公告)号：US08288238B2

    公开(公告)日：2012-10-16

    申请号：US13133643

    申请日：2010-09-25

    申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

    发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7391 ,  H01L29/66356

    摘要： The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.

    摘要翻译： 本发明公开了一种基于平面工艺自对准地制造隧道场效应晶体管（TFET）的方法，从而降低了用于制造平面TFET的光刻工艺的要求。 在该方法中，TFET的源极区域和漏极区域不直接由光刻法定义; 相反，它们由位于栅极的有源区域和两侧上并且不同于限定沟道区域的电介质膜的另一介电膜限定。 通过用蚀刻选择性地去除源极和漏极区域上的电介质膜，可以消除用于限定沟道区域，源极和漏极区域的三次光刻处理之间由于取向偏差的影响。 因此，可以基于该工艺自平面地制造平面TFET，从而减轻了在平面TFET的制造过程期间对光刻的对准偏差的刚性要求，这有助于制造具有稳定和可靠的平面TFET器件 特点

    METHOD FOR FABRICATING FINE LINE
    8.
    发明申请
    METHOD FOR FABRICATING FINE LINE 审中-公开
    细线生产方法

    公开(公告)号：US20120238097A1

    公开(公告)日：2012-09-20

    申请号：US13513852

    申请日：2011-09-29

    申请人： Ru Huang ,  Shuangshuang Pu ,  Yujie Ai ,  Zhihua Hao ,  Runsheng Wang

    发明人： Ru Huang ,  Shuangshuang Pu ,  Yujie Ai ,  Zhihua Hao ,  Runsheng Wang

    IPC分类号： H01L21/311

    CPC分类号： H01L21/3086 ,  B82Y30/00 ,  B82Y40/00 ,  H01L28/20

    摘要： Disclosed herein is a method for fabricating a fine line, which belongs to a field of ultra-large-scale integrated circuit manufacturing technology. In the invention, three trimming mask processes are performed to effectively improve a profile of the line and greatly reduce the LER (line edge roughness) of the line. At the same time, the invention is combined with a sidewall process, so that a nano-scaled fine line can be successfully fabricated and precisely controlled to 20 nm. Thus, a nano-scaled line with an optimized LER can be fabricated over the substrate.

    摘要翻译： 这里公开了一种属于超大规模集成电路制造技术领域的细线的制造方法。 在本发明中，执行三个修整掩模处理以有效地改善线的轮廓并大大降低线的LER（线边缘粗糙度）。 同时，本发明与侧壁工艺相结合，可以成功制作纳米级细线，精确控制为20nm。 因此，可以在衬底上制造具有优化的LER的纳米级线。

    Fabrication method of vertical silicon nanowire field effect transistor
    9.
    发明授权
    Fabrication method of vertical silicon nanowire field effect transistor 有权
    垂直硅纳米线场效应晶体管的制造方法

    公开(公告)号：US08592276B2

    公开(公告)日：2013-11-26

    申请号：US13501711

    申请日：2011-11-18

    申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

    发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L29/775

    摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

    摘要翻译： 本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。 与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力 ，并减少泄漏电流和漏极引起的屏障降低（DIBL）。 另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

    FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSISTOR
    10.
    发明申请
    FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSISTOR 有权
    垂直硅纳米管场效应晶体管的制造方法

    公开(公告)号：US20130011980A1

    公开(公告)日：2013-01-10

    申请号：US13501711

    申请日：2011-11-18

    申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

    发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

    IPC分类号： H01L21/336 ,  B82Y40/00

    CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L29/775

    摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

    摘要翻译： 本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。 与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力 ，并减少泄漏电流和漏极引起的屏障降低（DIBL）。 另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。