公开(公告)号：US5260603A

公开(公告)日：1993-11-09

申请号：US942136

申请日：1992-09-08

申请人： Mayumi Kamura ,  Souichi Imamura ,  Tatsuo Akiyama

发明人： Mayumi Kamura ,  Souichi Imamura ,  Tatsuo Akiyama

IPC分类号： H01L29/45 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L29/452 ,  H01L2924/0002

摘要： A semiconductor device having a GaAs substrate and an ohmic electrode. An electrode pad is on part of the ohmic electrode and on part of the GaAs substrate outside the ohmic electrode. The electrode pad includes a first platinum film, a titanium film, a second platinum film, and a gold film which are sequentially deposited on one another. The first platinum film is thinner than each of the titanium film, second platinum film and gold film.

摘要翻译： 具有GaAs衬底和欧姆电极的半导体器件。 电极焊盘位于欧姆电极的一部分上，并且在欧姆电极外部的部分GaAs衬底上。 电极焊盘包括彼此顺序沉积的第一铂膜，钛膜，第二铂膜和金膜。 第一铂膜比钛薄膜，第二铂膜和金膜薄。

公开(公告)号：US5717232A

公开(公告)日：1998-02-10

申请号：US632836

申请日：1996-04-16

申请人： Kazuhiko Inoue ,  Souichi Imamura ,  Masanori Ochi ,  Shigehiro Hosoi ,  Toru Suga ,  Takashi Kimura

发明人： Kazuhiko Inoue ,  Souichi Imamura ,  Masanori Ochi ,  Shigehiro Hosoi ,  Toru Suga ,  Takashi Kimura

IPC分类号： H01L21/338 ,  H01L23/29 ,  H01L23/31 ,  H01L23/66 ,  H01L29/812 ,  H01L29/80 ,  H01L23/58

CPC分类号： H01L23/66 ,  H01L23/293 ,  H01L23/3171 ,  H01L24/05 ,  H01L24/06 ,  H01L2223/6644 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48666 ,  H01L2224/48669 ,  H01L2224/49175 ,  H01L2224/85444 ,  H01L2224/85466 ,  H01L2224/85469 ,  H01L2224/8592 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/16152 ,  H01L2924/181

摘要： A semiconductor device has an active layer formed on a semiconductor substrate with different types of junctions, a source region, a drain region, a T-shaped gate electrode in which the cross-sectional area of the upper surface is larger than that of the lower surface, a first dielectric layer covering at least the exposed surface of the active layer, and the gate electrode, and a second dielectric layer enclosing the first dielectric layer. In the device, when the specific inductive capacities of the first and second dielectric layers are .epsilon.(1) and .epsilon.(2) respectively .epsilon.(1)

摘要翻译： 半导体器件具有形成在具有不同类型结的半导体衬底上的有源层，源极区，漏极区，T形栅电极，其中上表面的截面积大于下表面的横截面面积 表面，至少覆盖有源层的暴露表面的第一电介质层和栅电极，以及包围第一介电层的第二电介质层。 在该器件中，当第一和第二电介质层的比感应电容分别为ε（1）和ε（2）分别为ε（1）<ε（2）时，第一介电层的吸水率大于 第二电介质层的吸水率。

公开(公告)号：US5409849A

公开(公告)日：1995-04-25

申请号：US58684

申请日：1993-05-07

申请人： Yoshihiro Kishita ,  Masanori Ochi ,  Souichi Imamura ,  Toshikazu Fukuda

发明人： Yoshihiro Kishita ,  Masanori Ochi ,  Souichi Imamura ,  Toshikazu Fukuda

IPC分类号： H01L29/812 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L21/265

CPC分类号： H01L29/66863 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/66462

摘要： According to this invention, there is provided a method of manufacturing a compound semiconductor which can be formed at a high yield and in which variations in characteristics of elements caused by variations in distances between a source and a gate and between a drain and the gate can be minimized. In addition, there is provided a compound semiconductor device having a structure capable of increasing a power gain and obtaining a high-speed operation. According to this invention, an active layer is formed on a compound semi-conductor substrate, and source/drain electrodes are formed on the active layer to be separated from each other. The wall insulating films are respectively formed on side walls of the electrodes, and a gate electrode is formed between the side wall insulating films to be respectively in contact therewith.

摘要翻译： 根据本发明，提供一种制造化合物半导体的方法，该化合物半导体可以以高产率形成，并且由源极和栅极之间以及漏极和栅极之间的距离变化引起的元件的特性的变化可以 最小化 此外，提供了具有能够增加功率增益并获得高速操作的结构的化合物半导体器件。 根据本发明，在复合半导体基板上形成有源层，在有源层上形成源极/漏极，以分离。 壁绝缘膜分别形成在电极的侧壁上，并且在侧壁绝缘膜之间形成分别与其接触的栅电极。

公开(公告)号：US5204278A

公开(公告)日：1993-04-20

申请号：US853859

申请日：1992-03-20

申请人： Souichi Imamura ,  Toru Suga

发明人： Souichi Imamura ,  Toru Suga

IPC分类号： H01L21/265 ,  H01L21/338

CPC分类号： H01L29/66871 ,  H01L21/26553

摘要： After a silicon nitride film is deposited on a compound semiconductor substrate, another insulating film such as a silicon dioxide film is provided thereon so as to define a channel region in the semiconductor substrate. Impurity ions such as Si ions are selectively implanted into the semiconductor substrate in the presence of the silicon nitride film and the insulating film, thereby providing source and drain regions and the channel region therein. The insulating film and the silicon nitride film located above the channel region are successively removed to provide a Schottky gate electrode thereon. The silicon nitride film is selectively removed from the substrate surface to provide source and drain electrodes on their regions. Accordingly, MESFETs can be produced without exposing the substrate surface during its manufacture.

摘要翻译： 在化合物半导体衬底上沉积氮化硅膜之后，在其上设置诸如二氧化硅膜的另一绝缘膜，以在半导体衬底中限定沟道区。 在氮化硅膜和绝缘膜的存在下，将诸如Si离子的杂质离子选择性地注入到半导体衬底中，由此在其中提供源极和漏极区域以及沟道区域。 连续地去除位于沟道区上方的绝缘膜和氮化硅膜，以在其上提供肖特基栅电极。 从衬底表面选择性地去除氮化硅膜以在其区域上提供源电极和漏电极。 因此，可以在其制造期间不暴露衬底表面来制造MESFET。

公开(公告)号：US6061026A

公开(公告)日：2000-05-09

申请号：US21172

申请日：1998-02-10

申请人： Masanori Ochi ,  Souichi Imamura ,  Shigehiro Hosoi ,  Yutaka Ueno

发明人： Masanori Ochi ,  Souichi Imamura ,  Shigehiro Hosoi ,  Yutaka Ueno

IPC分类号： H01P11/00 ,  H01Q9/16 ,  H01Q9/28 ,  H01Q13/02 ,  H01Q13/08 ,  H01Q21/00 ,  H01Q21/06 ,  H01Q23/00 ,  H01Q1/38

CPC分类号： H01Q23/00 ,  H01Q21/0093 ,  H01Q21/064 ,  H01Q9/285

摘要： A high-gain monolithic antenna with high freedom of design has a signal circuit and a stripline dipole antenna which are provided on a substrate. A dielectric film and a conductor cover covering the dielectric film are provided on the upper surface of the substrate, in addition to a hole extending vertically downward to the underside of the substrate, a conductor wall being provided on the surface thereof. Furthermore, a metallic film is evaporated so as to contact both a metallic cover and a conductor wall. A first grounding conductor and a dielectric are provided on the lower surface of the substrate, and a second grounding conductor is provided on the upper surface of the substrate. A horn, which is tapered into the dielectric and the first grounding conductor thereby forming the shape of a quadrangular pyramid, is provided so as to overlap a hole etched into the substrate. Microwaves or milliwaves are radiated to/from the horn to/from the underside of the substrate.

摘要翻译： 具有高自由度的高增益单片天线具有设置在基板上的信号电路和带状线偶极子天线。 除了垂直向下延伸到基板的下侧的孔之外，还在基板的上表面上设置覆盖电介质膜的绝缘膜和导体盖，在其表面上设置有导体壁。 此外，金属膜被蒸发以与金属盖和导体壁接触。 第一接地导体和电介质设置在基板的下表面上，第二接地导体设置在基板的上表面上。 提供了锥形到电介质中的喇叭和第一接地导体，从而形成四角锥形的形状，以便与蚀刻到衬底中的孔重叠。 微波或毫瓦辐射到/从喇叭到基底的下面。

公开(公告)号：US5314844A

公开(公告)日：1994-05-24

申请号：US845945

申请日：1992-03-04

申请人： Souichi Imamura

发明人： Souichi Imamura

IPC分类号： B28D5/00 ,  H01L21/301 ,  H01L21/302 ,  H01S5/02 ,  H01L21/304

CPC分类号： B28D5/0005 ,  B28D5/0011 ,  H01L21/302 ,  H01S5/0201 ,  H01S5/0202 ,  Y10S148/028 ,  Y10T225/12

摘要： A method of dicing a wafer of III-V compound material without causing chipping and cracks. The method includes the steps of forming a scribe line on a surface of the wafer orthogonal to a crystal plane (011) by means of a scribing method, forming a groove in the semiconductor wafer in parallel to the crystal plane (011) by means of a grinding-cutting method, and breaking the semiconductor wafer along the scribe line and the groove.

摘要翻译： III-V复合材料的晶片切割而不引起切屑和裂纹的方法。 该方法包括以下步骤：通过划线方法在与晶面（011）正交的晶片的表面上形成刻划线，在半导体晶片中平行于晶体平面（011）形成沟槽，借助于 研磨切割方法，并且沿着划线和凹槽破坏半导体晶片。