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    Memory device having open bit line structure and method of sensing data therefrom
    1.
    发明申请
    Memory device having open bit line structure and method of sensing data therefrom 失效
    具有开放位线结构的存储器件和从其感测数据的方法

    公开(公告)号：US20070274122A1

    公开(公告)日：2007-11-29

    申请号：US11649273

    申请日：2007-01-04

    申请人： Su-A Kim ,  Ki-Whan Song

    发明人： Su-A Kim ,  Ki-Whan Song

    IPC分类号： G11C11/24

    CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/10897

    摘要： A memory device includes a plurality of memory blocks. Each memory block includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells provided at intersections of the bit lines and word lines; a plurality of capacitors, and a plurality of sense amplifiers. Each sense amplifier has a first input and a second input. The first input is connected to a first bit line of a first one of the memory blocks and is coupled via one of the capacitors to a first bit line of a second one of the memory blocks. The second input of the input is connected to a second bit line of the second one of the memory blocks and is coupled via one of the capacitors to a second bit line of the first one of the memory blocks.

    摘要翻译： 存储器件包括多个存储器块。 每个存储块包括多个位线，多个字线，设置在位线和字线的交点处的多个存储单元; 多个电容器和多个读出放大器。 每个读出放大器具有第一输入和第二输入。 第一输入端连接到第一个存储器块的第一位线，并通过一个电容器耦合到第二个存储器块的第一位线。 输入的第二输入连接到第二存储器块的第二位线，并且经由电容器中的一个耦合到第一个存储器块的第二位线。

    Memory device having open bit line structure and method of sensing data therefrom
    2.
    发明授权
    Memory device having open bit line structure and method of sensing data therefrom 失效
    具有开放位线结构的存储器件和从其感测数据的方法

    公开(公告)号：US07580314B2

    公开(公告)日：2009-08-25

    申请号：US11649273

    申请日：2007-01-04

    申请人： Su-A Kim ,  Ki-Whan Song

    发明人： Su-A Kim ,  Ki-Whan Song

    IPC分类号： G11C8/00

    CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/10897

    摘要： A memory device includes a plurality of memory blocks. Each memory block includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells provided at intersections of the bit lines and word lines; a plurality of capacitors, and a plurality of sense amplifiers. Each sense amplifier has a first input and a second input. The first input is connected to a first bit line of a first one of the memory blocks and is coupled via one of the capacitors to a first bit line of a second one of the memory blocks. The second input of the input is connected to a second bit line of the second one of the memory blocks and is coupled via one of the capacitors to a second bit line of the first one of the memory blocks.

    摘要翻译： 存储器件包括多个存储器块。 每个存储块包括多个位线，多个字线，设置在位线和字线的交点处的多个存储单元; 多个电容器和多个读出放大器。 每个读出放大器具有第一输入和第二输入。 第一输入端连接到第一个存储器块的第一位线，并通过一个电容器耦合到第二个存储器块的第一位线。 输入的第二输入连接到第二存储器块的第二位线，并且经由电容器中的一个耦合到第一个存储器块的第二位线。

    MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    5.
    发明申请
    MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    存储核心和半导体存储器件，包括它们

    公开(公告)号：US20120212989A1

    公开(公告)日：2012-08-23

    申请号：US13304851

    申请日：2011-11-28

    申请人： Hak-Soo YU ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    发明人： Hak-Soo YU ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    IPC分类号： G11C5/02

    CPC分类号： G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

    摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

    摘要翻译： 公开了一种半导体存储器件。 半导体存储器件包括存储器阵列块，第一字线和第二字线。 存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元 晶体管。 第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管 。

    Semiconductor memory device having improved bit line sensing operation and method for driving power in a bit line sense amplifier of the semiconductor memory device
    6.
    发明授权
    Semiconductor memory device having improved bit line sensing operation and method for driving power in a bit line sense amplifier of the semiconductor memory device 失效
    具有改进的位线检测操作的半导体存储器件和用于驱动半导体存储器件的位线读出放大器中的功率的方法

    公开(公告)号：US06859405B2

    公开(公告)日：2005-02-22

    申请号：US10465634

    申请日：2003-06-20

    申请人： Bum-Jae Lee ,  Su-A Kim ,  Kyu-Nam Lim

    发明人： Bum-Jae Lee ,  Su-A Kim ,  Kyu-Nam Lim

    IPC分类号： G11C11/4091 ,  G11C7/06 ,  G11C7/00

    CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C2207/065

    摘要： A semiconductor memory device having a bit line sense amplifier connected to a bit line pair may include a precharge part to precharge first and second drive nodes of the bit line sense amplifier to an equal voltage level. The device may include a switching part operatively connecting the first and second precharge nodes to the first and second drive nodes in response to sense amplifier drive signals applied during a data non-access mode. To drive power in the bit line sense amplifier, the precharge voltage may be applied in a precharge state to precharge the first and second drive nodes to the equal voltage level, the device may shift from the precharge state to an operational state to cut off the applied precharge voltage, and driving voltages may be applied to the first and second drive nodes to power the bit line sense amplifier of the device.

    摘要翻译： 具有连接到位线对的位线读出放大器的半导体存储器件可以包括预充电部分，以将位线读出放大器的第一和第二驱动节点预充电到相等的电压电平。 该装置可以包括切换部分，其响应于在数据非访问模式期间施加的读出放大器驱动信号，将第一和第二预充电节点可操作地连接到第一和第二驱动节点。 为了驱动位线读出放大器的电力，可以在预充电状态下施加预充电电压，以将第一和第二驱动节点预充电到等电压电平，器件可以从预充电状态转移到操作状态以切断 施加的预充电电压，并且可以向第一和第二驱动节点施加驱动电压以为器件的位线读出放大器供电。

    Semiconductor memory device including vertical channel transistors
    8.
    发明授权
    Semiconductor memory device including vertical channel transistors 有权
    半导体存储器件包括垂直沟道晶体管

    公开(公告)号：US08830715B2

    公开(公告)日：2014-09-09

    申请号：US13304851

    申请日：2011-11-28

    申请人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    发明人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    IPC分类号： G11C5/02 ,  G11C11/34 ,  H01L27/108 ,  G11C7/02 ,  G11C7/06

    CPC分类号： G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

    摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

    摘要翻译： 公开了一种半导体存储器件。 半导体存储器件包括存储器阵列块，第一字线和第二字线。 存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元 晶体管。 第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管 。