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    Semiconductor memory devices, memory systems including the same and method of writing data in the same
    4.
    发明授权
    Semiconductor memory devices, memory systems including the same and method of writing data in the same 有权
    半导体存储器件，包括相同的存储器系统和在其中写入数据的方法

    公开(公告)号：US09164834B2

    公开(公告)日：2015-10-20

    申请号：US14160614

    申请日：2014-01-22

    申请人： Hoi-ju Chung ,  Chul-sung Park ,  Jae-Wook Lee ,  Jang-Woo Ryu ,  Tae-seong Jang ,  Gong-heum Han

    发明人： Hoi-ju Chung ,  Chul-sung Park ,  Jae-Wook Lee ,  Jang-Woo Ryu ,  Tae-seong Jang ,  Gong-heum Han

    IPC分类号： G06F11/10 ,  G06F11/08 ,  G11C29/42

    CPC分类号： G06F11/1056 ,  G06F11/085 ,  G06F11/1008 ,  G11C29/42

    摘要： In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

    摘要翻译： 在一个实施例中，半导体器件包括存储器阵列和被配置为控制从存储器阵列读取数据和将数据写入存储器阵列的控制架构。 控制架构被配置为在存储器阵列中接收数据和码字位置，基于数据掩码选择所接收数据中的一个或多个数据单元，读取当前存储在存储器阵列中的码字位置处的码字，错误校正 读取码字以产生经校正的读取码字，从所选择的数据单元中选出的数据单元形成一个新的码字，并且将校验后的读取码字中的数据单元与所选择的数据单元不对应，并将新的代码字写入存储器阵列。

    Semiconductor memory devices and memory systems including the same
    5.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权

    公开(公告)号：US09767920B2

    公开(公告)日：2017-09-19

    申请号：US14798634

    申请日：2015-07-14

    申请人： Young-Il Kim ,  Hoi-ju Chung

    发明人： Young-Il Kim ,  Hoi-ju Chung

    IPC分类号： G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C11/401 ,  G11C29/04

    CPC分类号： G11C29/42 ,  G11C11/401 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0411

    摘要： A semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit, an error decision circuit and an error check and correction (ECC) circuit. The I/O gating circuit reads test pattern data to provide test result data in a test mode and reads a codeword in a normal mode. The error decision circuit determines the correctability of errors in the test result data by a first unit, based on the test pattern data and the test result data and provides a first error kind signal indicating a first determination result, in the test mode. The ECC circuit decodes the codeword including main data and parity data generated based on the main data, determines correctability of errors in the codeword by a second unit and provides a second error kind signal indicating a second determination result, in the normal mode. The main data includes a plurality of unit data.

    Memory devices that perform masked write operations and methods of operating the same
    6.
    发明授权
    Memory devices that perform masked write operations and methods of operating the same 有权
    执行屏蔽写操作的内存设备及其操作方法

    公开(公告)号：US09588840B2

    公开(公告)日：2017-03-07

    申请号：US14225686

    申请日：2014-03-26

    申请人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

    发明人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

    IPC分类号： G06F11/10 ,  G06F11/32

    CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

    摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

    摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。