公开(公告)号：US5590035A

公开(公告)日：1996-12-31

申请号：US354168

申请日：1994-12-08

申请人： Takehiko Shimomura ,  Takashi Miyake

发明人： Takehiko Shimomura ,  Takashi Miyake

IPC分类号： G06F13/12 ,  G05B19/042 ,  G06F15/78 ,  G05B11/01

CPC分类号： G05B19/0423 ,  G05B2219/21117 ,  G05B2219/25369 ,  G05B2219/25409

摘要： An output control circuit capable of reducing a time lag at the time of switching connection of a flip-flop 3 and port latch 2, which output PWM waveforms, with an input/output terminal 5 to provide a more real-time control, and increasing the control accuracy, by setting data specifying a port latch 2 or flip-flop 3 which is a signal source to be connected next with an input/output terminal in an operation mode reload register 7 beforehand, and reloading the data directly to an operation mode register 4 by means of a reload signal RL.

摘要翻译： 一种输出控制电路，其能够在输入/输出端子5切换输出PWM波形的触发器3和端口锁存器2的连接时减少时间延迟，以提供更实时的控制，并且增加 控制精度通过预先在操作模式重新加载寄存器7中设定指定接下来与输入/输出端子连接的信号源的端口锁存器2或触发器3的数据，并将数据直接重新加载到操作模式 寄存器4通过重载信号RL。

公开(公告)号：US4668569A

公开(公告)日：1987-05-26

申请号：US800157

申请日：1985-11-20

申请人： Kojiro Ito ,  Kunio Murakami ,  Minoru Kishida ,  Takehiko Shimomura

发明人： Kojiro Ito ,  Kunio Murakami ,  Minoru Kishida ,  Takehiko Shimomura

IPC分类号： C08J5/18 ,  C08L67/00 ,  B32B5/16 ,  B32B27/08 ,  B32B27/36

CPC分类号： C08J5/18 ,  C08L67/00 ,  C08J2367/00 ,  Y10T428/25 ,  Y10T428/251 ,  Y10T428/256 ,  Y10T428/257 ,  Y10T428/31786

摘要： A matte film made of a composition comprising (a) from 3 to 20 parts by weight of a polyarylate resin made of terephthalic acid, isophthalic acid (the molar ratio of the terephthalic acid group to the isophthalic acid group being from 9:1 to 1:9) and a bivalent phenolic compound, (b) from 60 to 94 parts by weight of a linear polyester resin and (c) from 3 to 30 parts by weight of a styrene resin or an acrylic resin, and satisfying the following condition:A-10.ltoreq.S.ltoreq.A+15where A is the parts by weight of the polyarylate resin and S is the parts by weight of the styrene resin or acrylic resin, and said film being stretched at least 1.5 times in at least one direction.

摘要翻译： 一种由以下组合物制成的无光泽膜：（a）3〜20重量份由对苯二甲酸，间苯二甲酸（对苯二甲酸与间苯二甲酸的摩尔比为9:1〜1）的聚芳酯树脂 ：9）和二价酚类化合物，（b）60〜94重量份线性聚酯树脂和（c）3〜30重量份苯乙烯树脂或丙烯酸树脂，满足以下条件： A-10

公开(公告)号：US06819580B2

公开(公告)日：2004-11-16

申请号：US10356537

申请日：2003-02-03

申请人： Masayuki Konishi ,  Takehiko Shimomura

发明人： Masayuki Konishi ,  Takehiko Shimomura

IPC分类号： G11C506

CPC分类号： G11C5/14 ,  G11C5/066 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C2207/105

摘要： A semiconductor chip is provided, with which presence of dead pins can be easily noticed and a process for controlling the potential at dead pins can be performed easily. An input/output controller (IOC) for coordinating the input/output of signals through individual pins (PN1 to PN8) includes an input/output buffer (BFa) and the input/output buffer (BFa) includes a switch (SW4a) and a switch (SW4b). A setting memory (STMa) for storing settings for control of the input/output of signals in the input/output buffer (BFa) contains a memory table and the memory table contains an item about the dead pin potential control process so that a power-supply potential (Vdd) or a ground potential (GND) can be applied to the dead pins, i.e. the fourth pin (PN4) and the fifth pin (PN4).

摘要翻译： 提供了一种半导体芯片，可以容易地看到死针的存在，并且可以容易地执行用于控制死针的电位的处理。 用于通过各个引脚（PN1至PN8）协调信号的输入/输出的输入/输出控制器（IOC）包括输入/​​输出缓冲器（BFa），输入/输出缓冲器（BFa）包括开关（SW4a）和 开关（SW4b）。 用于存储用于控制输入/输出缓冲器（BFa）中的信号的输入/输出的设置的设置存储器（STMa）包含存储表，并且存储表包含关于死端电位控制处理的项目， 供电电位（Vdd）或接地电位（GND）可以施加到死针，即第四针（PN4）和第五针（PN4）。

公开(公告)号：US06674153B2

公开(公告)日：2004-01-06

申请号：US10163508

申请日：2002-06-07

申请人： Takehiko Shimomura ,  Katsuyoshi Watanabe

发明人： Takehiko Shimomura ,  Katsuyoshi Watanabe

IPC分类号： H01L23552

CPC分类号： H01L24/06 ,  G01R31/2884 ,  G01R31/302 ,  G01R31/305 ,  G01R31/308 ,  H01L22/32 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2224/45099

摘要： A semiconductor device has: an inner active region 3 including a first electronic circuit formed on a semiconductor substrate; an outer active region 4 positioned between the edges 2a, 2b of the semiconductor substrate 2 and the inner active region 3 and including a second electronic circuit formed on the semiconductor substrate 2; a main bonding pad 6a for assembly formed inside a region where the inner active region 3 is opposed to the outer active region 4 and formed along the outer periphery of the inner active region 3; a sub-bonding pad 7 for analysis formed outside the opposing region 5 where the inner active region 3 is opposed to the outer active region 4; and a pad-to-pad interconnection wiring 8 for connecting the main bonding pad 6a to the sub-bonding pad 7.

摘要翻译： 半导体器件具有：内部有源区域3，其包括形成在半导体衬底上的第一电子电路; 位于半导体衬底2的边缘2a，2b和内部有源区域3之间并且包括形成在半导体衬底2上的第二电子电路的外部有源区域4; 在内侧有源区域3与内部有源区域3的外周形成的区域内形成有用于组装的主焊盘6a; 在内部有源区域3与外部有源区域4相对的相对区域5的外部形成用于分析的子接合焊盘7; 以及用于将主焊盘6a连接到子接合焊盘7的焊盘对焊盘互连布线8。

公开(公告)号：US6091351A

公开(公告)日：2000-07-18

申请号：US76073

申请日：1998-05-12

申请人： Takehiko Shimomura

发明人： Takehiko Shimomura

IPC分类号： G06F3/00 ,  H03K3/356 ,  H03K19/0185 ,  H03M1/12

CPC分类号： H03K3/356121 ,  H03K3/356113

摘要： An analog section (4) including the selector for analog input terminals, ladder resistors, a decoder for decoding the output of the ladder resistors, a chopper amplifier, and a sample and hold circuit, is operated by 5 V power-supply system. A digital section (5) that generates a control signal for controlling the operation of the analog section 4 is operated by 3.3 V power-supply system. No design change of a sensor connected from outside a microcomputer is required.

摘要翻译： 包括用于模拟输入端子的选择器，梯形电阻器，用于解码梯形电阻器的输出的解码器，斩波放大器和采样和保持电路的模拟部分（4）由5V电源系统操作。 产生用于控制模拟部分4的操作的控制信号的数字部分（5）由3.3V电源系统操作。 不需要从微型计算机外部连接的传感器的设计变更。

公开(公告)号：US06865703B2

公开(公告)日：2005-03-08

申请号：US09939602

申请日：2001-08-28

申请人： Takehiko Shimomura ,  Masayuki Konishi

发明人： Takehiko Shimomura ,  Masayuki Konishi

IPC分类号： G01R31/28 ,  G01R31/316 ,  G01R31/3185 ,  H01L21/822 ,  H01L27/04 ,  H03K19/00

CPC分类号： G01R31/318536 ,  G01R31/318572 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a scan test system comprising: a semiconductor device including a scan register connected between an input/output pin on an analog input side and an internal system logic; a semiconductor device including a scan register connected between an input/output pin on an analog output side and an analog sensor; and an analog wiring connecting the input/output pins each other. Thus, the scan register can be chained to thereby constitute a boundary scan register chain, and thereby JTAG control can be carried out by use of TAPC. Therefore, monitoring inspection where probes are set up by high-density-assembling of semiconductor devices and the multiple pins of low-cost devices, can be achieved.

摘要翻译： 提供了一种扫描测试系统，包括：半导体器件，包括连接在模拟输入侧的输入/输出引脚和内部系统逻辑之间的扫描寄存器; 包括连接在模拟输出侧的输入/输出引脚与模拟传感器之间的扫描寄存器的半导体器件; 以及将输入/输出引脚彼此连接的模拟布线。 因此，可以将扫描寄存器链接从而构成边界扫描寄存器链，从而可以通过使用TAPC来进行JTAG控制。 因此，可以实现通过高密度组装半导体器件和低成本器件的多个引脚来建立探针的监视检查。

公开(公告)号：US06789174B2

公开(公告)日：2004-09-07

申请号：US09983481

申请日：2001-10-24

申请人： Masayuki Konishi ,  Takehiko Shimomura

发明人： Masayuki Konishi ,  Takehiko Shimomura

IPC分类号： G06F1300

CPC分类号： G06F13/4243

摘要： In a memory access device, a memory address space of a Random Access Memory (RAM) is divided into blocks BK0 to BKn having continuous address areas. Address buses and data buses of a Central Processing Unit (CPU) and a Real Time Debugger (RTD) are connected to each of the blocks BK0 to BKn. The memory access control circuit checks whether memory blocks accessed by the CPU and the RTD are the same. The memory access control circuit permits simultaneous access by the CPU and the RTD to the memory blocks when the memory block accessed by the CPU and the RTD are not same.

摘要翻译： 在存储器访问装置中，随机存取存储器（RAM）的存储器地址空间被划分为具有连续地址区域的块BK0至BKn。 每个块BK0至BKn连接中央处理单元（CPU）和实时调试器（RTD）的地址总线和数据总线。 存储器访问控制电路检查由CPU和RTD访问的存储器块是否相同。 当由CPU和RTD访问的存储器块不相同时，存储器访问控制电路允许CPU和RTD同时访问存储器块。

公开(公告)号：US6150886A

公开(公告)日：2000-11-21

申请号：US266793

申请日：1999-03-12

申请人： Takehiko Shimomura

发明人： Takehiko Shimomura

IPC分类号： H03L7/087 ,  H03L7/07 ,  H03L7/089 ,  H03L7/18 ,  H03L7/22 ,  H03L7/23

CPC分类号： H03L7/0805 ,  H03L7/07 ,  H03L7/18 ,  H03L7/23 ,  H03L7/0891

摘要： A PLL circuit including multiple sets of phase locked loops, each of which has a phase comparator, a charge pump, a low pass filter, as oscillator, a clock generator and a frequency divider. The various oscillators of the multiple sets each have a different oscillation frequency. The clock generator generates a multiphase clock signal from a single phase clock signal generated by the oscillator. The PLL circuit generates multiple single phase clock signals and multiphase clock signals without need to tune the oscillation frequency of the VCOs over a wide range. The noise of the PLL is reduced since each VCO covers a smaller range of oscillation frequencies.

摘要翻译： PLL电路包括多组锁相环，每组具有相位比较器，电荷泵，低通滤波器，作为振荡器，时钟发生器和分频器。 多组的各种振荡器各具有不同的振荡频率。 时钟发生器由振荡器产生的单相时钟信号产生多相时钟信号。 PLL电路产生多个单相时钟信号和多相时钟信号，无需在较宽范围内调谐VCO的振荡频率。 PLL的噪声减小，因为每个VCO覆盖较小的振荡频率范围。

公开(公告)号：US07028123B2

公开(公告)日：2006-04-11

申请号：US10411222

申请日：2003-04-11

申请人： Takehiko Shimomura

发明人： Takehiko Shimomura

IPC分类号： G06F13/24

CPC分类号： G06F11/24 ,  G01R31/3016 ,  G01R31/31701 ,  G06F13/24

摘要： In a microcomputer, a testing-purpose interrupt request signal generator generates a testing-purpose interrupt request signal, an interrupt request selecting register stores an interrupt request selection signal for making an interrupt request during testing effective, and at least one delay circuit generates one or more delayed interrupt request selection signals obtained by delaying the interrupt request selection signal by one or more delay times. Each of selection circuits selects either one of the interrupt request signals or the testing-purpose interrupt request signal based on the delayed interrupt request selection signal. The testing-purpose interrupt request signals output from the respective selection circuits at a different timing, can be sequentially input to the interrupt controller.

摘要翻译： 在微型计算机中，测试目的中断请求信号发生器产生测试用途中断请求信号，中断请求选择寄存器存储用于在测试期间产生中断请求的中断请求选择信号，并且至少一个延迟电路产生一个或 通过将中断请求选择信号延迟一个或多个延迟时间而获得的延迟中断请求选择信号。 每个选择电路基于延迟的中断请求选择信号选择中断请求信号或测试用途中断请求信号中的任何一个。 可以在不同的定时从各个选择电路输出的测试用途中断请求信号顺序地输入到中断控制器。

公开(公告)号：US06711708B1

公开(公告)日：2004-03-23

申请号：US09377630

申请日：1999-08-19

申请人： Takehiko Shimomura

发明人： Takehiko Shimomura

IPC分类号： G01R3128

CPC分类号： G01R31/318541 ,  G01R31/318536

摘要： There is provided a boundary-scan test device incorporated into a semiconductor integrated circuit for running self-diagnostics on the semiconductor integrated circuit. The device comprises a bypass unit for, when a package in which the semiconductor integrated circuit is assembled does not have one or more corresponding external input/output pins associated with one or more predetermined boundary-scan registers, changing the length of a boundary-scan register chain that consists of a plurality of boundary-scan registers by bypassing the one or more predetermined boundary-scan registers according to a bypass control signal applied thereto.

摘要翻译： 提供了一种结合到半导体集成电路中的边界扫描测试装置，用于在半导体集成电路上运行自诊断。 该装置包括旁路单元，用于当其中组装半导体集成电路的封装不具有与一个或多个预定边界扫描寄存器相关联的一个或多个对应的外部输入/输出引脚时，改变边界扫描的长度 寄存器链，其由多个边界扫描寄存器组成，通过绕过一个或多个预定边界扫描寄存器，根据施加到其上的旁路控制信号。