公开(公告)号：US5401988A

公开(公告)日：1995-03-28

申请号：US974322

申请日：1992-11-10

申请人： Tsuneaki Kudou ,  Hiroyuki Watanabe

发明人： Tsuneaki Kudou ,  Hiroyuki Watanabe

IPC分类号： H01L21/822 ,  G11C5/00 ,  G11C5/06 ,  G11C8/14 ,  G11C11/41 ,  H01L21/82 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  H01L27/15

CPC分类号： H01L27/0207 ,  G11C11/41 ,  G11C5/00 ,  G11C5/063 ,  G11C8/14

摘要： A large scale standard cell is provided with at least three power source wires and at least two circuit-element-arranging areas interposed therebetween, whereby the lateral length of the cell can be flexibly reduced to owing delay due to wire resistance and capacity and to reduce the area of the cell or the entire area of a circuit pattern composed therewith. The vertical direction of the cell is optionally changeable in one cell row.

摘要翻译： 大规模的标准电池具有至少三个电源线和插入其间的至少两个电路元件布置区域，由此电池的横向长度可以灵活地减少到由于导线电阻和容量导致的延迟，并且减少 单元的区域或由其组成的电路图案的整个区域。 单元格行的垂直方向可选地在一个单元格行中可变。

公开(公告)号：US5173864A

公开(公告)日：1992-12-22

申请号：US722379

申请日：1991-06-26

申请人： Hiroyuki Watanabe ,  Tsuneaki Kudou

发明人： Hiroyuki Watanabe ,  Tsuneaki Kudou

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A standard cell for standard-cell type integrated circuits, designed with a computer, includes a basic functional circuit, for example, a flip-flop circuit and a signal delay circuit connected to the basic functional circuit. The signal delay circuit is located within the standard cell along with the basic functional circuit. The design allows the timing of the integrated circuit to be adjusted without changing the geometry of the integrated circuit.

摘要翻译： 用计算机设计的标准单元型集成电路的标准单元包括基本功能电路，例如触发电路和连接到基本功能电路的信号延迟电路。 信号延迟电路与基本功能电路一起位于标准单元内。 该设计允许在不改变集成电路的几何形状的情况下调整集成电路的时序。

公开(公告)号：US5363494A

公开(公告)日：1994-11-08

申请号：US964886

申请日：1992-10-22

申请人： Tsuneaki Kudou

发明人： Tsuneaki Kudou

IPC分类号： G06F13/36 ,  G06F3/00 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4018

摘要： A first bus wiring line to which a plurality of first circuits each having the same bit range are connected, a second bus wiring line to which a plurality of second circuits each having a bit range smaller than that of each of the first circuits are connected, and a bus interface circuit having a buffer circuit connected between a portion of the first bus wiring line and the second bus wiring line and a dummy buffer circuit connected to the remaining portion of the first bus wiring line are arranged in an integrated circuit. Fox this reason, when a plurality of circuits having different bit ranges are connected to the bus wiring lines, the loads of the bus wiring lines can be made uniform, and a data transfer operation through the bus lines can be performed at a high speed. The operating frequency of a clock can be increased, and the performance of the system can be improved.

摘要翻译： 连接具有相同比特范围的多个第一电路的第一总线布线，连接有比第一电路的位数小的多个第二电路的第二总线布线， 并且具有连接在第一总线布线和第二总线布线的一部分之间的缓冲电路的总线接口电路和连接到第一总线布线的剩余部分的虚拟缓冲电路布置在集成电路中。 这个原因，当具有不同位范围的多个电路连接到总线布线时，可以使总线布线的负载均匀，并且可以高速地执行通过总线的数据传送操作。 可以提高时钟的工作频率，提高系统的性能。

公开(公告)号：US5359212A

公开(公告)日：1994-10-25

申请号：US950731

申请日：1992-09-24

申请人： Tsuneaki Kudou ,  Takeji Tokumaru

发明人： Tsuneaki Kudou ,  Takeji Tokumaru

IPC分类号： H01L27/02 ,  H01L27/10

CPC分类号： H01L27/0207

摘要： An integrated circuit with circuit layout enabling higher area utilization efficiency and shorter routing lengths, suitable for large-scale integrated, high-speed processing applications. The integrated circuit includes at least one function block for performing desired functions with respect to input data entered in a first direction to produce output data in the first direction; and at least two control blocks for providing control signals for controlling the operations of the function block, in a second direction perpendicular to the first direction, the control blocks being arranged such that the function block is located between two of the control blocks.

摘要翻译： 具有电路布局的集成电路，可实现更高的面积利用效率和更短的路由长度，适用于大规模集成，高速处理应用。 集成电路包括至少一个功能块，用于执行关于在第一方向上输入的输入数据的期望功能，以产生第一方向的输出数据; 以及至少两个控制块，用于在垂直于第一方向的第二方向上提供用于控制功能块的操作的控制信号，控制块被布置成使得功能块位于两个控制块之间。

公开(公告)号：US5631910A

公开(公告)日：1997-05-20

申请号：US243517

申请日：1994-05-16

申请人： Yasuyuki Nozuyama ,  Tsuneaki Kudou

发明人： Yasuyuki Nozuyama ,  Tsuneaki Kudou

IPC分类号： G01R31/28 ,  G06F11/22 ,  G06F11/267 ,  H01L21/66 ,  G06F11/00

CPC分类号： G06F11/2236

摘要： An information processing system composed of a plurality of circuit blocks operative in an normal operation mode and in a self-diagnosis mode comprises: a clock signal generating circuit for generating a basic clock signal in the normal operation mode, and a first clock signal with a period. N times (N=2, 3, . . . ) as long as that of the basic clock signal and a second clock signal out of phase from the first clock signal by a delay less than one cycle of the first clock signal in the self-diagnosis mode; a memory for storing microinstructions for self-diagnosis operative in synchronism with the basic clock signal in the normal operation mode, and in synchronism with the first clock signal in the self-diagnosis mode; a decoder for inputting and decoding the mlcroinstructions for self-diagnosis stored in the memory; a test data generating circuit for generating test data in accordance with the decoded results obtained by the decoder in synchronism with the first clock signal at the self-diagnosis mode; first type circuit blocks operative in synchronism with the basic clock in the normal operation mode, for storing test data generated by said test data generating means In synchronism with the second clock and outputting test data therein In synchronism with the first clock In the self-diagnosis mode; second type circuit blocks for outputting output data corresponding to the test data provided in synchronism with the basic clock signal in the normal operation mode, and in synchronism with the first clock in the self-diagnosis mode; and a signature compressing circuit for inputting the test resultant data outputted from the circuit blocks to diagnose the operation of the circuit blocks, in synchronism with the second clock signal in the self-diagnosis mode.

摘要翻译： 由在正常操作模式和自诊断模式下操作的多个电路块组成的信息处理系统包括：用于在正常操作模式下产生基本时钟信号的时钟信号发生电路和具有正常操作模式的第一时钟信号 期。 N次（N = 2,3，...），只要基本时钟信号和第二时钟信号与第一时钟信号异相延迟小于自身中的第一时钟信号的一个周期的延迟 诊断模式; 存储器，用于存储与正常操作模式中的基本时钟信号同步操作的自诊断微指令，并且与自诊断模式中的第一时钟信号同步; 用于输入和解码存储在存储器中的用于自诊断的mlcroinstructions的解码器; 测试数据产生电路，用于根据在自诊断模式下与第一时钟信号同步地由解码器获得的解码结果产生测试数据; 用于存储由所述测试数据产生装置产生的测试数据与第二时钟同步并在其中输出测试数据的第一类型电路块与正常操作模式中的基本时钟同步操作。与第一时钟同步在自诊断中 模式; 第二类型电路块，用于在正常操作模式中输出与基本时钟信号同步提供的测试数据相对应的输出数据，并且与自诊断模式中的第一时钟同步; 以及签名压缩电路，用于输入从电路块输出的测试结果数据，以与自诊断模式中的第二时钟信号同步地诊断电路块的操作。

公开(公告)号：US5373480A

公开(公告)日：1994-12-13

申请号：US182553

申请日：1994-01-18

申请人： Tsuneaki Kudou

发明人： Tsuneaki Kudou

IPC分类号： G11C17/18 ,  G11C7/18 ,  G11C8/12 ,  G11C17/12 ,  G11C13/00

CPC分类号： G11C7/18 ,  G11C17/12 ,  G11C8/12

摘要： A read only memory includes a memory cell matrix, a word line decoder, a column decoder, and an output buffer. Said memory cell matrix is comprised of a plurality of submatrices, each of which is formed by dividing bit lines into a plurality of parts. Each sub-matrix contains the same word lines. Said word line decoder produces a signal to select a certain sub-matrix in addition to signals to select a certain word line. Said column decoder produces signals to select one column from each of said sub-matrix. Said output buffer has a column selection circuit having a plurality of stages. The first stage selects one column from each of said sub-matrices according to said signals from said column decoder. The second stage selects one column among said selected columns according to said signal to select a certain sub-matrix produced in said word line decoder. Thus, a particular memory cell is selected from the memory cell matrix. In this case, the number of memory cell transistors connected to each bit line is greatly reduced. The data readout speed of this ROM is, therefore, greatly improved in this invention.

摘要翻译： 只读存储器包括存储单元矩阵，字线解码器，列解码器和输出缓冲器。 所述存储单元矩阵由多个子矩阵组成，每个子矩阵通过将位线分成多个部分而形成。 每个子矩阵包含相同的字线。 所述字线解码器产生除了选择特定字线的信号之外还选择特定子矩阵的信号。 所述列解码器产生信号以从每个所述子矩阵中选择一列。 所述输出缓冲器具有多级的列选择电路。 第一级根据来自所述列解码器的所述信号从每个所述子矩阵中选择一列。 第二级根据所述信号在所选择的列中选择一列，以选择在所述字线解码器中产生的特定子矩阵。 因此，从存储单元矩阵中选择特定存储单元。 在这种情况下，连接到每个位线的存储单元晶体管的数量大大减少。 因此，在本发明中，该ROM的数据读出速度大大提高。

公开(公告)号：US5329477A

公开(公告)日：1994-07-12

申请号：US943561

申请日：1992-09-11

申请人： Tsuneaki Kudou

发明人： Tsuneaki Kudou

IPC分类号： G06F7/505 ,  G06F7/50 ,  G06F7/506

CPC分类号： G06F7/505

摘要： Disclosed herein is an adder which comprises a Manchester-type adder circuit and which can operate as fast as a dynamic adder, and can perform addition during the clock cycle as a static dynamic adder. Hence, the adder serves to increase the operating frequency of the system in which it is incorporated. The adder further comprises two initializing signal output circuits, each designed to generate an initializing signal in response to predetermined data supplied before the Manchester-type adder circuit starts performing each operation, thereby to initialize the Manchester-type adder circuit.

摘要翻译： 这里公开了一种加法器，其包括曼彻斯特式加法器电路，其可以像动态加法器一样运行，并且可以在时钟周期期间作为静态动态加法器执行相加。 因此，加法器用于增加其并入的系统的工作频率。 加法器还包括两个初始化信号输出电路，每个初始化信号输出电路被设计成响应于在曼彻斯特式加法器电路开始执行每个操作之前提供的预定数据产生初始化信号，从而初始化曼彻斯特式加法器电路。

公开(公告)号：US5173626A

公开(公告)日：1992-12-22

申请号：US712541

申请日：1991-06-10

申请人： Tsuneaki Kudou ,  Naoko Nakamura

发明人： Tsuneaki Kudou ,  Naoko Nakamura

IPC分类号： G01R31/28 ,  G06F11/267 ,  H01L21/66 ,  H03K3/037 ,  H03K17/693

CPC分类号： G06F11/2236 ,  H03K17/693 ,  H03K3/0372

摘要： An improved flip-flop with a scan path comprises a front page circuit driven in response to a clock signal and multiplexers for receiving a data signal and a scan test signal. Each of the multiplexers comprises a single stage of FETs connected in series between a power source and a ground. This arrangement can remarkably improve an operation frequency.

摘要翻译： 具有扫描路径的改进的触发器包括响应时钟信号驱动的前置电路和用于接收数据信号和扫描测试信号的多路复用器。 每个复用器包括在电源和地之间串联连接的单级FET。 这种布置可以显着提高操作频率。

公开(公告)号：US5130941A

公开(公告)日：1992-07-14

申请号：US622969

申请日：1990-12-06

申请人： Tsuneaki Kudou

发明人： Tsuneaki Kudou

IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/76 ,  G11C19/38

CPC分类号： G11C19/38 ,  G06F5/015

摘要： A dynamic barrel shifter has a data input portion, a data shift portion, and a shifted data output portion including sense inverters which are set at threshold voltage higher than a half of the power source voltage. The sense inverters are provided for every transmission route for each binary code. The dynamic barrel shifter also has a pre-charge portion for pre-charging the data shift portion and the shifted data output portion prior to the input of data. The pre-charge portion includes a first power source voltage applying circuit for applying electric potential lower than the power source voltage to the data shift portion through first gate elements from the power source, and a second power source voltage applying circuit for applying electric potential equal to the power source voltage to the input side of the shifted data output portion through second gate elements.

公开(公告)号：US5059830A

公开(公告)日：1991-10-22

申请号：US435932

申请日：1989-11-14

申请人： Takeji Tokumaru ,  Tsuneaki Kudou ,  Kazuyuki Omote

发明人： Takeji Tokumaru ,  Tsuneaki Kudou ,  Kazuyuki Omote

IPC分类号： G06F3/00 ,  G06F13/40 ,  H03K17/687 ,  H03K19/094 ,  H04L25/02

CPC分类号： H04L25/028 ,  G06F13/4072 ,  H03K19/09429

摘要： A bus driver in which at least two P channel MOS transistors and at least two N channel MOS transistors are employed and these are respectively connected in series. A data signal is inputted into a gate of one of the P channel MOS transistors, an inverted input of an enable signal is inputted into a gate of the other of the P channel MOS transistors, the enable signal is inputted into a gate of one of the N channel MOS transistors and the data signal is also inputted into a gate of the other of the N channel MOS transistors. Further, an output signal is outputted from a connection point of the P channel MOS transistors and the N channel MOS transistors. Also disclosed is another embodiment of a bus driver in which an inverted signal of an enable signal is inputted into the other of the P channel MOS transistors through an inverter.