公开(公告)号：US08633601B2

公开(公告)日：2014-01-21

申请号：US13383727

申请日：2010-07-13

申请人： Nitesh Kumbhat ,  Abhishek Choudhury ,  Venkatesh V. Sundaram ,  Rao R. Tummala

发明人： Nitesh Kumbhat ,  Abhishek Choudhury ,  Venkatesh V. Sundaram ,  Rao R. Tummala

IPC分类号： H01L23/52

CPC分类号： H01L24/81 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/15788 ,  H05K3/305 ,  H05K3/323 ,  H05K3/3436 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

摘要： The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

摘要翻译： 本发明的各种实施例提供细间距，芯片到衬底互连组件，以及制造和使用组件的方法。 组件通常包括具有管芯焊盘和设置在其上的凸块的半导体和其上设置有衬底焊盘的衬底。 凸起构造成当凸块与衬底焊盘接触时将半导体的至少一部分与衬底的至少一部分电互连。 此外，当凸块与衬底焊盘接触时，凸起的至少一部分和衬底焊盘的至少一部分变形，从而在它们之间产生非冶金结合。

公开(公告)号：US20120106117A1

公开(公告)日：2012-05-03

申请号：US13285912

申请日：2011-10-31

申请人： Venkatesh V. Sundaram ,  Rao R. Tummala

发明人： Venkatesh V. Sundaram ,  Rao R. Tummala

IPC分类号： H05K1/18 ,  H01L23/498 ,  H05K1/11 ,  H01L23/48

CPC分类号： H05K1/141 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10515 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05647

摘要： A 3D interconnect structure comprising an ultra-thin interposer having a plurality of ultra-high density of through-via interconnections defined therein. The 3D interposer electrically connects first and second electronic devices in vertical dimension and has the same or similar through-via density as the first or second electronic devices it connects. The various embodiments of the interconnect structure allows 3D ICs to be stacked with or without TSVs and increases bandwidth between the two electronic devices as compared to other interconnect structures of the prior art. Further, the interconnect structure of the present invention is scalable, testable, thermal manageable, and can be manufactured at relatively low costs. Such a 3D structure can be used for a wide variety of applications that require a variety of heterogeneous ICs, such as logic, memory, graphics, power, wireless and sensors that cannot be integrated into single ICs.

摘要翻译： 一种3D互连结构，其包括具有限定在其中的多个超高密度通孔互连的超薄插入器。 3D插入器在垂直方向上电连接第一和第二电子设备，并且具有与其连接的第一或第二电子设备相同或相似的通孔密度。 与现有技术的其它互连结构相比，互连结构的各种实施例允许3D IC与或不具有TSV堆叠并增加两个电子器件之间的带宽。 此外，本发明的互连结构是可扩展的，可测试的，可热控制的，并且可以以相对低的成本制造。 这种3D结构可用于需要各种异构IC（例如逻辑，存储器，图形，功率，无线和不能集成到单个IC中的传感器）的各种应用中。

公开(公告)号：US09167694B2

公开(公告)日：2015-10-20

申请号：US13285912

申请日：2011-10-31

申请人： Venkatesh V. Sundaram ,  Rao R. Tummala

发明人： Venkatesh V. Sundaram ,  Rao R. Tummala

IPC分类号： H05K1/11 ,  H05K7/02 ,  H05K1/14 ,  H01L23/498 ,  H01L25/065 ,  H01L21/768 ,  H01L23/367 ,  H01L25/18 ,  H05K3/34

CPC分类号： H05K1/141 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10515 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05647

摘要： A 3D interconnect structure comprising an ultra-thin interposer having a plurality of ultra-high density of through-via interconnections defined therein. The 3D interposer electrically connects first and second electronic devices in vertical dimension and has the same or similar through-via density as the first or second electronic devices it connects. The various embodiments of the interconnect structure allows 3D ICs to be stacked with or without TSVs and increases bandwidth between the two electronic devices as compared to other interconnect structures of the prior art. Further, the interconnect structure of the present invention is scalable, testable, thermal manageable, and can be manufactured at relatively low costs. Such a 3D structure can be used for a wide variety of applications that require a variety of heterogeneous ICs, such as logic, memory, graphics, power, wireless and sensors that cannot be integrated into single ICs.

摘要翻译： 一种3D互连结构，其包括具有限定在其中的多个超高密度通孔互连的超薄插入器。 3D插入器在垂直方向上电连接第一和第二电子设备，并且具有与其连接的第一或第二电子设备相同或相似的通孔密度。 与现有技术的其它互连结构相比，互连结构的各种实施例允许3D IC与或不具有TSV堆叠并增加两个电子器件之间的带宽。 此外，本发明的互连结构是可扩展的，可测试的，可热控制的，并且可以以相对低的成本制造。 这种3D结构可用于需要各种异构IC（例如逻辑，存储器，图形，功率，无线和不能集成到单个IC中的传感器）的各种应用中。

公开(公告)号：US08970036B2

公开(公告)日：2015-03-03

申请号：US13825815

申请日：2011-09-20

申请人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venkatesh V. Sundaram ,  Rao R. Tummala ,  Xian Qin

发明人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venkatesh V. Sundaram ,  Rao R. Tummala ,  Xian Qin

IPC分类号： H01L23/48 ,  H01L23/00 ,  H05K3/34 ,  H05K3/40 ,  H05K1/02

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/3436 ,  H05K3/4007 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00

摘要： Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.

摘要翻译： 提供了一种应力消除的二级互连结构，其低成本并适应低TCE封装和印刷电路板（PCB）之间的热膨胀系数（TCE）不匹配。 所述互连结构至少包括第一焊盘，支撑柱和焊料凸块，其中第一焊盘和支撑柱可操作以吸收基本上所有的塑性应变，从而增强两个电子部件之间的顺应性。

公开(公告)号：US20120261805A1

公开(公告)日：2012-10-18

申请号：US13448064

申请日：2012-04-16

申请人： VENKATESH V. SUNDARAM ,  Fuhan Liu ,  Rao R. Tummala ,  Qiao Chen

发明人： VENKATESH V. SUNDARAM ,  Fuhan Liu ,  Rao R. Tummala ,  Qiao Chen

IPC分类号： H01L23/495 ,  H01L21/768

CPC分类号： H01L23/147 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： The various embodiments of the present invention provide a low cost, low electrical loss, and low stress panel-based silicon interposer with TPVs. The interposer of the present invention has a thickness of about 100 microns to 200 microns and such thickness is achieved without utilizing a carrier and further wherein no grinding, bonding, or debonding methods are utilized, therefore distinguishing the interposer of the present invention from prior art embodiments.

摘要翻译： 本发明的各种实施例提供了具有TPV的低成本，低电损耗和低应力面板的硅插入器。 本发明的插入件具有约100微米至200微米的厚度，并且在不使用载体的情况下实现这样的厚度，并且其中不使用研磨，粘合或剥离方法，因此区分本发明的插入件与现有技术 实施例。