公开(公告)号：US10699986B2

公开(公告)日：2020-06-30

申请号：US16233266

申请日：2018-12-27

Applicant: ABB Schweiz AG

Inventor： Daniel Kearney ,  Jürgen Schuderer ,  Slavo Kicin ,  Liliana Duarte

IPC: H01L23/34 ,  H01L23/473 ,  H01L25/07 ,  H05K1/02 ,  H01L23/538 ,  H05K1/18

Abstract: An electronics package includes an electrically conducting support layer; at least one electrically conducting outer layer; at least two power electronics components arranged on different sides of the support layer and electrically interconnected with the support layer and with the at least one outer layer; and isolation material, in which the support layer and the at least two power electronics components are embedded, the support layer and the at least one outer layer are laminated together with the isolation material; and a cooling channel for conducting a cooling fluid through the electronics package, the cooling channel runs between the at least two power electronics components through the support layer.

公开(公告)号：US20190131211A1

公开(公告)日：2019-05-02

申请号：US16233266

申请日：2018-12-27

Applicant: ABB Schweiz AG

Inventor： Daniel Kearney ,  Jürgen Schuderer ,  Slavo Kicin ,  Liliana Duarte

IPC: H01L23/473 ,  H01L25/07 ,  H05K1/02

Abstract: An electronics package includes an electrically conducting support layer; at least one electrically conducting outer layer; at least two power electronics components arranged on different sides of the support layer and electrically interconnected with the support layer and with the at least one outer layer; and isolation material, in which the support layer and the at least two power electronics components are embedded, the support layer and the at least one outer layer are laminated together with the isolation material; and a cooling channel for conducting a cooling fluid through the electronics package, the cooling channel runs between the at least two power electronics components through the support layer.

公开(公告)号：US20180040526A1

公开(公告)日：2018-02-08

申请号：US15666858

申请日：2017-08-02

Applicant: ABB Schweiz AG ,  Audi AG

Inventor： Jürgen Schuderer ,  Umamaheswara Vemulapati ,  Marco Bellini ,  Jan Vobecky

IPC: H01L23/14 ,  H01L25/18 ,  H01L23/538 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L23/147 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/535 ,  H01L23/5386 ,  H01L23/62 ,  H01L25/072 ,  H01L25/18 ,  H01L29/0634 ,  H01L29/0646 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

公开(公告)号：US20190304946A1

公开(公告)日：2019-10-03

申请号：US16442923

申请日：2019-06-17

Applicant: ABB Schweiz AG ,  AUDI AG

Inventor： Didier Cottet ,  Felix Traub ,  Jürgen Schuderer ,  Andreas Apelsmeier ,  Johann Asam

IPC: H01L23/00 ,  H01L25/07 ,  H01L23/64

Abstract: A power semiconductor module, including a housing; a power semiconductor chip within the housing; power terminals protruding from the housing and electrically interconnected with power electrodes of the semiconductor chip; and auxiliary terminals protruding from the housing and electrically interconnected with a gate electrode and one of the power electrodes; wherein three auxiliary terminals are arranged in a coaxial auxiliary terminal arrangement, which comprises an inner and two outer auxiliary terminals, which are arranged on opposing sides of the inner auxiliary terminal. The inner auxiliary terminal is electrically interconnected with the gate electrode or one of the power electrodes and the two outer auxiliary terminals are electrically connected with the other one of the gate electrode and the one of the power electrodes.

公开(公告)号：US20190273040A1

公开(公告)日：2019-09-05

申请号：US16419668

申请日：2019-05-22

Applicant: ABB Schweiz AG ,  Audi AG

Inventor： Fabian Mohn ,  Chunlei Liu ,  Jürgen Schuderer

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semi-manufactured power semiconductor module includes a substrate for bonding at least one power semiconductor chip; a first leadframe bonded to the substrate and providing power terminals; and a second leadframe bonded to the substrate and providing auxiliary terminals; wherein the first leadframe and/or the second leadframe include an interlocking element adapted for aligning the first leadframe and the second leadframe with respect to each other and/or with respect to a mold for molding an encapsulation around the substrate, the first leadframe and the second leadframe.

公开(公告)号：US11189556B2

公开(公告)日：2021-11-30

申请号：US16419668

申请日：2019-05-22

Applicant: ABB Schweiz AG ,  Audi AG

Inventor： Fabian Mohn ,  Chunlei Liu ,  Jürgen Schuderer

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

Abstract: A semi-manufactured power semiconductor module includes a substrate for bonding at least one power semiconductor chip; a first leadframe bonded to the substrate and providing power terminals; and a second leadframe bonded to the substrate and providing auxiliary terminals; wherein the first leadframe and/or the second leadframe include an interlocking element adapted for aligning the first leadframe and the second leadframe with respect to each other and/or with respect to a mold for molding an encapsulation around the substrate, the first leadframe and the second leadframe.

公开(公告)号：US11018109B2

公开(公告)日：2021-05-25

申请号：US16442923

申请日：2019-06-17

Applicant: ABB Schweiz AG ,  AUDI AG

Inventor： Didier Cottet ,  Felix Traub ,  Jürgen Schuderer ,  Andreas Apelsmeier ,  Johann Asam

IPC: H01L23/64 ,  H01L23/49 ,  H01L23/00 ,  H01L25/07 ,  H01L23/498

Abstract: A power semiconductor module, including a housing; a power semiconductor chip within the housing; power terminals protruding from the housing and electrically interconnected with power electrodes of the semiconductor chip; and auxiliary terminals protruding from the housing and electrically interconnected with a gate electrode and one of the power electrodes; wherein three auxiliary terminals are arranged in a coaxial auxiliary terminal arrangement, which comprises an inner and two outer auxiliary terminals, which are arranged on opposing sides of the inner auxiliary terminal. The inner auxiliary terminal is electrically interconnected with the gate electrode or one of the power electrodes and the two outer auxiliary terminals are electrically connected with the other one of the gate electrode and the one of the power electrodes.

公开(公告)号：US20200066686A1

公开(公告)日：2020-02-27

申请号：US16673427

申请日：2019-11-04

Applicant: ABB Schweiz AG ,  Audi AG

Inventor： Fabian Mohn ,  Felix Traub ,  Jürgen Schuderer

IPC: H01L25/07 ,  H01L23/498 ,  H01L23/538 ,  H02M7/00 ,  H05K7/14 ,  H01L23/00

Abstract: A half-bridge module includes a substrate with a base metallization layer divided into a first DC conducting area, a second DC conducting area and an AC conducting area; at least one first power semiconductor switch chip bonded to the first DC conducting area and electrically interconnected with the AC conducting area; at least one second power semiconductor switch chip bonded to the AC conducting area and electrically interconnected with the second DC conducting area; and a coaxial terminal arrangement including at least one inner DC terminal, the at least first outer DC terminal and the at least one second outer DC terminal protrude from the module and are arranged in a row, such that the at least one inner DC terminal is coaxially arranged between the at least one first outer DC terminal and the at least one second outer DC terminal; wherein the at least one inner DC terminal is electrically connected to the second DC conducting area; the at least one first outer DC terminal and the at least one second outer DC terminal are electrically connected to the first DC conducting area; and the at least one first outer DC terminal and the at least one second outer DC terminal are electrically interconnected with an electrically conducting bridging element which is adapted for distributing at least a half of the load current between the at least one first outer DC terminal and the at least one second outer DC terminal.

公开(公告)号：US10079193B2

公开(公告)日：2018-09-18

申请号：US15453123

申请日：2017-03-08

Applicant: ABB Schweiz AG ,  Audi AG

Inventor： Fabian Mohn ,  Jürgen Schuderer

IPC: H01L23/22 ,  H01L23/24 ,  H01L23/367 ,  H01L23/498 ,  H01L23/31 ,  H01L23/04 ,  H01L23/373 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/3675 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2225/1017 ,  H01L2225/1023 ,  H01L2225/1047 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0665 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/186 ,  H05K1/0263 ,  H05K1/115 ,  H05K3/325 ,  H05K3/368 ,  H05K7/1432 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2203/1316 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor module comprises a semiconductor device; a substrate, on which the semiconductor device is attached; a molded encasing, into which the semiconductor device and the substrate are molded; at least one power terminal partially molded into the encasing and protruding from the encasing, which power terminal is electrically connected with the semiconductor device; and an encased circuit board at least partially molded into the encasing and protruding over the substrate in an extension direction of the substrate, wherein the encased circuit board comprises at least one receptacle for a pin, the receptacle being electrically connected via the encased circuit board with a control input of the semiconductor device.

公开(公告)号：US20170263527A1

公开(公告)日：2017-09-14

申请号：US15453123

申请日：2017-03-08

Applicant: ABB Schweiz AG ,  Audi AG

Inventor： Fabian Mohn ,  Jürgen Schuderer

IPC: H01L23/367 ,  H01L23/31 ,  H01L25/10 ,  H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L23/04

CPC classification number: H01L23/3675 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L25/162 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2225/1017 ,  H01L2225/1047 ,  H01L2225/1094 ,  H01L2924/0665 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/186 ,  H05K1/0263 ,  H05K1/115 ,  H05K3/325 ,  H05K3/368 ,  H05K7/1432 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2203/1316 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor module comprises a semiconductor device; a substrate, on which the semiconductor device is attached; a molded encasing, into which the semiconductor device and the substrate are molded; at least one power terminal partially molded into the encasing and protruding from the encasing, which power terminal is electrically connected with the semiconductor device; and an encased circuit board at least partially molded into the encasing and protruding over the substrate in an extension direction of the substrate, wherein the encased circuit board comprises at least one receptacle for a pin, the receptacle being electrically connected via the encased circuit board with a control input of the semiconductor device.