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    Power throttling in a multicore system
    4.
    发明授权
    Power throttling in a multicore system 有权

    公开(公告)号：US11048323B2

    公开(公告)日：2021-06-29

    申请号：US16397888

    申请日：2019-04-29

    Applicant: Apple Inc.

    Inventor： Ching Elizabeth Ho ,  Hao Chen ,  Nitin Bhargava ,  Syed F. Ali

    IPC: G06F1/329 ,  G06F1/3228

    Abstract: An apparatus includes a plurality of processor cores, a cache memory that includes a plurality of banks, and a power management circuit. The power management circuit is configured to maintain a power credit approach for the apparatus that includes tracking a total number of currently available power credits, and to store a plurality of threshold values. Each threshold value is associated with one or more of a plurality of throttling actions. In response to the total number of currently available power credits reaching a particular threshold value of the plurality of threshold values, the power management circuit performs the one or more throttling actions associated with the particular threshold value. The plurality of throttling actions includes selectively throttling one or more of the plurality of processor cores, and selectively throttling one or more of the plurality of banks in the cache memory.

    Coordinate based QoS escalation
    5.
    发明授权
    Coordinate based QoS escalation 有权
    基于协调的QoS升级

    公开(公告)号：US09472169B2

    公开(公告)日：2016-10-18

    申请号：US14258662

    申请日：2014-04-22

    Applicant: Apple Inc.

    Inventor： Hao Chen ,  Benjamin K. Dodge ,  Peter F. Holland

    IPC: G06T1/20 ,  G09G5/397 ,  G09G5/00 ,  G09G5/14

    CPC classification number: G09G5/397 ,  G09G5/001 ,  G09G5/14 ,  G09G2340/0407 ,  G09G2340/10 ,  G09G2350/00 ,  G09G2352/00 ,  G09G2360/125

    Abstract: Systems and methods for determining priorities of pixel fetch requests of separate requestors in a display control unit. The distance between the oldest pixel in an output buffer and the output equivalent coordinate of the oldest outstanding source pixel read request for each requestor in the display control unit is calculated. Then, a priority is assigned to each requestor based on this calculated distance. If a given requestor lags behind the other requestors based on a comparison of the distance between the oldest pixel and the output equivalent coordinate of the oldest outstanding source pixel read, then source pixel fetch requests for this given requestor are given a higher priority than source pixel fetch requests for the other requestors.

    Abstract translation: 用于确定显示控制单元中单独请求者的像素提取请求的优先级的系统和方法。 计算输出缓冲器中的最旧像素与显示控制单元中每个请求者的最早未完成源像素读取请求的输出等效坐标之间的距离。 然后，基于该计算出的距离将优先级分配给每个请求者。 如果给定的请求者基于最旧的像素读取的最旧的源像素的输出等效坐标之间的距离的比较而落在其他请求者之后，则给予该给定请求者的源像素提取请求被给予比源像素更高的优先级 提取其他请求者的请求。

    N-DIMENSIONAL COLLAPSIBLE FIFO
    6.
    发明申请
    N-DIMENSIONAL COLLAPSIBLE FIFO 审中-公开
    N维可缩放FIFO

    公开(公告)号：US20140237195A1

    公开(公告)日：2014-08-21

    申请号：US13771861

    申请日：2013-02-20

    Applicant: APPLE INC.

    Inventor： Peter F. Holland ,  Hao Chen ,  Albert C. Kuo

    IPC: G06F5/06

    CPC classification number: G06F5/10 ,  G06F2205/106

    Abstract: A system and method for efficient dynamic utilization of shared resources. A computing system includes a shared data structure accessed by multiple requestors. Both indications of access requests and indices pointing to entries within the data structure are stored in storage buffers. Each storage buffer maintains at a selected end an oldest stored indication of an access request from a respective requestor. Each storage buffer stores information for the respective requestor in an in-order contiguous manner beginning at the selected end. The indices stored in a given storage buffer are updated responsive to allocating new data or deallocating stored data in the shared data structure. Entries in a storage buffer are deallocated in any order and remaining entries are collapsed toward the selected end to eliminate gaps left by the deallocated entry.

    Abstract translation: 一种有效动态利用共享资源的系统和方法。 计算系统包括由多个请求者访问的共享数据结构。 访问请求的指示和指向数据结构内的条目的索引都存储在存储缓冲区中。 每个存储缓冲器在选定的端保持来自相应请求者的最早存储的访问请求的指示。 每个存储缓冲器以从所选择的端开始的按顺序的连续方式存储针对各个请求者的信息。 响应于分配新数据或释放在共享数据结构中存储的数据来更新存储在给定存储缓冲器中的索引。 存储缓冲区中的条目以任何顺序取消分配，剩余条目将朝向选定的端部折叠，以消除已解除分配条目留下的空白。

    EFFICIENT PROCESSING OF ACCESS REQUESTS FOR A SHARED RESOURCE
    7.
    发明申请
    EFFICIENT PROCESSING OF ACCESS REQUESTS FOR A SHARED RESOURCE 审中-公开
    有效地处理共享资源的访问请求

    公开(公告)号：US20140085320A1

    公开(公告)日：2014-03-27

    申请号：US13629049

    申请日：2012-09-27

    Applicant: APPLE INC

    Inventor： Peter F. Holland ,  Hao Chen

    IPC: G06F12/00 ,  G09G5/39

    CPC classification number: G06F13/1663

    Abstract: A system and method for efficiently processing access requests for a shared resource. A computing system includes a shared memory accessed by multiple requestors. Control logic determines two requestors seek to access a same data block within the shared memory. In response to the determination, a first requestor of the two requestors sends a read request to the shared memory on behalf of the two requestors. The second requestor of the two requestors is prevented from sending a read request. In response to detecting data is returned as a response to the read request generated by the first requestor, both the first requestor and the second requestor retrieve the data. In response to detecting a given requestor of the two requestors generates an indication that it is unable to continue retrieving the same response data, the two requestors return to generating separate, respective read requests.

    Abstract translation: 一种用于有效地处理共享资源的访问请求的系统和方法。 计算系统包括由多个请求者访问的共享存储器。 控制逻辑确定两个请求者寻求访问共享存储器内的相同数据块。 响应于该确定，两个请求者的第一请求者代表两个请求者向共享存储器发送读请求。 两个请求者的第二请求者被阻止发送读请求。 响应于检测数据作为对由第一请求者产生的读取请求的响应而返回，第一请求者和第二请求者都检索数据。 响应于检测到两个请求者的给定请求者产生不能继续检索相同响应数据的指示，两个请求者返回产生单独的相应读请求。

    QoS-Aware Scheduling
    8.
    发明申请
    QoS-Aware Scheduling 审中-公开
    QoS感知调度

    公开(公告)号：US20140006743A1

    公开(公告)日：2014-01-02

    申请号：US14017971

    申请日：2013-09-04

    Applicant: Apple Inc.

    Inventor： Sukalpa Biswas ,  Hao Chen

    IPC: G06F9/50

    CPC classification number: G06F9/5033 ,  G06F13/1668

    Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

    Abstract translation: 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

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