公开(公告)号：US20150221596A1

公开(公告)日：2015-08-06

申请号：US14173807

申请日：2014-02-05

Applicant: APPLIED MATERIALS, INC.

Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Mei-Yee SHEK ,  Yana Cheng ,  Sree Rangasai V. Kesapragada

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

Abstract translation: 描述了用于半导体器件的互连结构及其制造方法。 该方法包括将基板定位在真空处理室中。 衬底具有暴露的铜表面和暴露的低k电介质表面。 在铜表面上形成金属层，但不在低k电介质表面上。 在金属层和低k电介质层上形成金属基介电层。

公开(公告)号：US10170299B2

公开(公告)日：2019-01-01

申请号：US15186436

申请日：2016-06-18

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik ,  Yong Cao ,  Yana Cheng ,  Weifeng Ye

IPC: H01L21/02 ,  H01L21/768

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

公开(公告)号：US10109520B2

公开(公告)日：2018-10-23

申请号：US15285011

申请日：2016-10-04

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. Kesapragada ,  Kevin Moraes ,  Srinivas Guggilla ,  He Ren ,  Mehul Naik ,  David Thompson ,  Weifeng Ye ,  Yana Cheng ,  Yong Cao ,  Xianmin Tang ,  Paul F. Ma ,  Deenesh Padhi

IPC: H01L21/768 ,  H01L21/02

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US10546742B2

公开(公告)日：2020-01-28

申请号：US16237407

申请日：2018-12-31

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik ,  Yong Cao ,  Yana Cheng ,  Weifeng Ye

IPC: H01L21/02 ,  H01L21/768

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

公开(公告)号：US09984976B2

公开(公告)日：2018-05-29

申请号：US15041454

申请日：2016-02-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Yana Cheng ,  Yong Cao ,  Srinivas Guggilla ,  Sree Rangasai Kesapragada ,  Xianmin Tang ,  Deenesh Padhi

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  C23C14/0036 ,  C23C14/0676 ,  C23C14/352 ,  H01J37/32504 ,  H01J37/3408 ,  H01J37/3455 ,  H01L21/02145 ,  H01L21/02266 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.

公开(公告)号：US11056325B2

公开(公告)日：2021-07-06

申请号：US16215769

申请日：2018-12-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Thanh X. Nguyen ,  Alexander Jansen ,  Yana Cheng ,  Randal Schmieding ,  Yong Cao ,  Xianmin Tang ,  William Johanson

IPC: H01J37/34 ,  C23C14/34 ,  C23C14/54 ,  H01J37/32

Abstract: A movable substrate support with a top surface for holding a substrate, when present, is used in conjunction with a cover ring that is stationary to adjust for a shadow effect to control substrate edge uniformity during deposition processes. The cover ring is held stationary by an electrically isolated spacer that engages with a grounded shield in the process volume of a semiconductor process chamber. A controller adjusts the substrate support in response to deposition material on a top surface of the cover ring to maintain the shadow effect and substrate edge uniformity.

公开(公告)号：US09299605B2

公开(公告)日：2016-03-29

申请号：US14201728

申请日：2014-03-07

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik ,  Yong Cao ,  Sree Rangasai V. Kesapragada ,  Mei-Yee Shek ,  Yana Cheng

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/76841 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/321 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849

Abstract: Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Abstract translation: 提供了在形成在互连结构中的绝缘材料中的金属线层上形成钝化保护结构的方法。 在一个实施例中，用于在半导体器件的互连结构中的金属线上形成钝化保护的方法包括在处理中形成在基板上的互连结构中的介电体绝缘层界定的金属线上选择性地形成金属覆盖层 结合在多腔室处理系统中，在处理室中的基底上原位形成阻挡层; 其中所述阻挡层是金属介电层，并且在所述多室处理系统中的阻挡层上形成电介质覆盖层。

公开(公告)号：US10707122B2

公开(公告)日：2020-07-07

申请号：US16140342

申请日：2018-09-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. Kesapragada ,  Kevin Moraes ,  Srinivas Guggilla ,  He Ren ,  Mehul Naik ,  David Thompson ,  Weifeng Ye ,  Yana Cheng ,  Yong Cao ,  Xianmin Tang ,  Paul F. Ma ,  Deenesh Padhi

IPC: H01L21/768 ,  H01L21/32 ,  H01L21/02 ,  H01L21/3105

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US10665426B2

公开(公告)日：2020-05-26

申请号：US14986168

申请日：2015-12-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Yana Cheng ,  Zhefeng Li ,  Chi Hong Ching ,  Yong Cao ,  Rongjun Wang

IPC: H01J37/32 ,  C23C14/00 ,  H01J37/34

Abstract: Methods are disclosed for depositing a thin film of compound material on a substrate. In some embodiments, a method of depositing a layer of compound material on a substrate include: flowing a reactive gas into a plasma processing chamber having a substrate to be sputter deposited disposed therein in opposition to a sputter target comprising a metal; exciting the reactive gas into a reactive gas plasma to react with the sputter target and to form a first layer of compound material thereon; flowing an inert gas into the plasma processing chamber; and exciting the inert gas into a plasma to sputter a second layer of the compound material onto the substrate directly from the first layer of compound material. The cycles of target poisoning and sputtering may be repeated until a compound material layer of appropriate thickness has been formed on the substrate.

公开(公告)号：US09633839B2

公开(公告)日：2017-04-25

申请号：US14744688

申请日：2015-06-19

Applicant: APPLIED MATERIALS, INC.

Inventor： Weimin Zeng ,  Thanh X. Nguyen ,  Yana Cheng ,  Yong Cao ,  Daniel Lee Diehl ,  Srinivas Guggilla ,  Rongjun Wang ,  Xianmin Tang

IPC: H01L21/02

CPC classification number: H01L21/0234 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02266

Abstract: In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.