公开(公告)号：US07226868B2

公开(公告)日：2007-06-05

申请号：US10492541

申请日：2002-10-31

申请人： Aelan Mosden ,  Sandra Hyland ,  Minori Kajimoto

发明人： Aelan Mosden ,  Sandra Hyland ,  Minori Kajimoto

IPC分类号： H01L21/302

CPC分类号： H01L21/67069 ,  H01J37/32082 ,  H01J37/3244 ,  H01J2237/3341 ,  H01L21/3065

摘要： A plasma processing system for and method of utilizing an improved etch chemistry for effectively etching high aspect ratio silicon features. The process chemistry employs precursor gases suitable for producing a fluorine/chlorine etch chemistry as well as precursor gases suitable for forming chemical bonds of sufficient strength to create stable feature side-walls. The improved process chemistries include SO2/SF4/SiCl4, SO2/SF4/Cl2, SO2/SiF4/SiCl4, SO2SIF4/Cl2, O2/F2/Cl2, N2 O/F2/Cl2, and NO2/F2/Cl2-based chemistries.

摘要翻译： 一种等离子体处理系统以及利用改进的蚀刻化学品来有效地蚀刻高纵横比硅特征的方法。 工艺化学使用适用于生产氟/氯蚀刻化学品的前体气体，以及适于形成足够强度的化学键的前体气体，以产生稳定的特征侧壁。 改进的工艺化学物质包括SO 2 SO 3 / SF 4 / SiCl 4，SO 2 / SF 4 2/2/2/2 / SiF 4 / SiCl 4，SO 2 2/3/2/2/2/2/2/2 的化学物质。

公开(公告)号：US20130228842A1

公开(公告)日：2013-09-05

申请号：US13601076

申请日：2012-08-31

申请人： Takahiro Kotou ,  Hideto Takekida ,  Minori Kajimoto

发明人： Takahiro Kotou ,  Hideto Takekida ,  Minori Kajimoto

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/7889 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

摘要： A semiconductor storage device includes a semiconductor substrate. A first insulating film is provided on the semiconductor substrate. A charge storage layer includes a first part provided on the first insulating film, an intermediate insulating film provided on the first part, and a second part provided on the intermediate insulating film, and is capable of storing electric charges. A second insulating film is provided on an upper surface and a side surface of the charge storage layer. A control gate is opposed to the upper surface and the side surface of the charge storage layer via the second insulating film, and is configured to control a voltage of the charge storage layer. The intermediate insulating film is recessed in comparison with side surfaces of the first and second parts on the side surface of the charge storage layer.

摘要翻译： 半导体存储装置包括半导体基板。 第一绝缘膜设置在半导体衬底上。 电荷存储层包括设置在第一绝缘膜上的第一部分，设置在第一部分上的中间绝缘膜和设置在中间绝缘膜上的第二部分，并且能够存储电荷。 第二绝缘膜设置在电荷存储层的上表面和侧表面上。 控制栅极经由第二绝缘膜与电荷存储层的上表面和侧表面相对，并且被配置为控制电荷存储层的电压。 与电荷储存层的侧表面上的第一和第二部分的侧表面相比，中间绝缘膜凹陷。

公开(公告)号：US08390076B2

公开(公告)日：2013-03-05

申请号：US12420363

申请日：2009-04-08

申请人： Atsuhiro Suzuki ,  Hiroshi Shimode ,  Takeshi Shimane ,  Norihisa Arai ,  Minori Kajimoto

发明人： Atsuhiro Suzuki ,  Hiroshi Shimode ,  Takeshi Shimane ,  Norihisa Arai ,  Minori Kajimoto

IPC分类号： H01L21/70

CPC分类号： H01L27/0207 ,  H01L21/823425 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括：半导体衬底; 在半导体基板上形成岛状形状的有源区域; 围绕有源区域并包括形成在半导体衬底上的元件隔离槽和嵌入元件隔离槽中的元件隔离膜的元件隔离区; 栅极绝缘膜各自形成在相应的一个有源区上，并且具有第一端部，该第一端部从相应的有源区域突出到一侧的元件隔离区域和从相应的有源区域突出到元件隔离区域上的第二端部 在另一侧，其中第一端部的突出端具有与第二端部的突出部的长度不同的长度。

公开(公告)号：US08377720B2

公开(公告)日：2013-02-19

申请号：US11419079

申请日：2006-05-18

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Hiroyuki Nitta

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Hiroyuki Nitta

IPC分类号： H01L21/00

CPC分类号： H01L27/088 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed.

摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成不同厚度的栅极绝缘膜的工艺，沉积构成栅电极的膜，去除在包括晶体管的晶体管的杂质扩散区域表面上形成的具有不同厚度的栅极绝缘膜 栅极电极和将杂质掺杂到去除栅极绝缘膜的部分中。

公开(公告)号：US08193058B2

公开(公告)日：2012-06-05

申请号：US12638754

申请日：2009-12-15

申请人： Yugo Ide ,  Minori Kajimoto

发明人： Yugo Ide ,  Minori Kajimoto

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： A semiconductor device including a semiconductor substrate; a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor provided with a first gate electrode including a floating gate electrode comprising a polycrystalline silicon layer of a first thickness, a control gate electrode provided above the floating gate electrode, and an inter-gate insulating film between the floating and the control gate electrode; a pair of select gate transistors on the semiconductor substrate with a pair of second gate electrodes neighboring in alignment with the first gate electrode, each second gate electrode including a lower-layer gate electrode comprising the polycrystalline silicon layer of the first thickness, an upper-layer gate electrode provided above the lower-layer gate electrode; a polyplug of the first thickness situated between the second gate electrodes of the pair of select gate transistors; and a metal plug provided on the polyplug.

摘要翻译： 一种半导体器件，包括半导体衬底; 在半导体衬底上沿预定方向排列的多个存储单元晶体管，每个存储单元晶体管设置有第一栅电极，该第一栅电极包括包括第一厚度的多晶硅层的浮置栅电极，设置在浮置栅极上方的控制栅电极 电极和浮栅与控制栅电极之间的栅间绝缘膜; 一对选择栅极晶体管，其具有与第一栅电极相对的一对第二栅电极，每个第二栅电极包括包含第一厚度的多晶硅层的下层栅电极， 设置在下层栅极电极上方的层间栅电极; 位于所述一对选择栅晶体管的第二栅电极之间的第一厚度的聚拢块; 以及设置在息肉上的金属塞。

公开(公告)号：US07651924B2

公开(公告)日：2010-01-26

申请号：US12233052

申请日：2008-09-18

申请人： Hiroshi Kawamoto ,  Naoki Kai ,  Koichi Matsuno ,  Minori Kajimoto

发明人： Hiroshi Kawamoto ,  Naoki Kai ,  Koichi Matsuno ,  Minori Kajimoto

IPC分类号： H01L21/76 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/3125 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/316 ,  H01L21/76229 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of fabricating a semiconductor device includes applying a coating oxide film to a surface of a substrate including a semiconductor substrate so that a recess formed in the surface is filled with the coating oxide film, applying a steam oxidation treatment to the substrate at a first temperature, soaking the substrate in heated water while applying a megasonic wave to the substrate in the heated water, and applying a steam oxidation treatment to the substrate at a second temperature higher than the first temperature.

摘要翻译： 一种制造半导体器件的方法包括将涂覆氧化物膜施加到包括半导体衬底的衬底的表面，使得在表面中形成的凹部填充有涂覆氧化物膜，在第一衬底上施加蒸汽氧化处理 温度，将基底浸入加热的水中，同时在加热的水中向基底施加兆声波，并在高于第一温度的第二温度下对基底进行蒸汽氧化处理。

公开(公告)号：US20090140316A1

公开(公告)日：2009-06-04

申请号：US12277448

申请日：2008-11-25

申请人： Takashi Sugihara ,  Minori Kajimoto

发明人： Takashi Sugihara ,  Minori Kajimoto

IPC分类号： H01L21/28 ,  H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes an insulating film formed on a semiconductor substrate, a plurality of active areas formed on the insulating film from a semiconductor layer which is formed integrally with the substrate through openings of the insulating film, the active areas being formed by being divided into a striped shape by a plurality of trenches reaching an upper surface of the insulating film, the active areas having upper surfaces and sides respectively, a first gate insulating film formed so as to cover the upper surfaces and sides of the active areas, a charge trap layer having a face located on the first gate insulating film and confronting the upper surfaces and the sides of the active areas with the first gate insulating film being interposed therebetween, a second gate insulating film formed on the charge trap layer, and a gate electrode formed on the second gate insulating film.

摘要翻译： 一种半导体存储器件，包括形成在半导体衬底上的绝缘膜，形成在绝缘膜上的多个有源区，该绝缘膜与半导体层形成，该半导体层通过绝缘膜的开口与衬底一体形成，有源区通过分割形成 通过多个沟槽到达绝缘膜的上表面的条纹形状，所述有源区域分别具有上表面和侧面，形成为覆盖有源区域的上表面和侧面的第一栅极绝缘膜，电荷 捕获层，其具有位于所述第一栅极绝缘膜上的面并且与所述有源区的上表面和所述侧面间隔开所述第一栅极绝缘膜，形成在所述电荷陷阱层上的第二栅极绝缘膜，以及栅电极 形成在第二栅绝缘膜上。

公开(公告)号：US20050051831A1

公开(公告)日：2005-03-10

申请号：US10890132

申请日：2004-07-14

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

摘要翻译： 非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

公开(公告)号：US08008703B2

公开(公告)日：2011-08-30

申请号：US12175201

申请日：2008-07-17

申请人： Mitsuhiro Noguchi ,  Minori Kajimoto

发明人： Mitsuhiro Noguchi ,  Minori Kajimoto

IPC分类号： H01L29/788

CPC分类号： H01L27/11546 ,  H01L27/105 ,  H01L27/11526

摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.

摘要翻译： 非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱 ，其包括围绕第一阱的侧部区域的第一部分和围绕第一阱的下部区域的第二部分，并且将第一阱与半导体衬底以及第二导电类型的第三阱电隔离， 其形成在半导体衬底中。 第三井具有比第二井的第二部分更少的深度。

公开(公告)号：US07800157B2

公开(公告)日：2010-09-21

申请号：US12174090

申请日：2008-07-16

申请人： Akihiro Ryusenji ,  Minori Kajimoto ,  Yugo Ide

发明人： Akihiro Ryusenji ,  Minori Kajimoto ,  Yugo Ide

IPC分类号： H01L29/94

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device including: sequentially forming a first insulating film, a first electrode film, a second insulating film, and a second electrode film on a substrate; forming a groove that separates the second electrode film, the second insulating film and the first electrode film; forming an insulating film inside the groove so that an upper surface thereof is positioned between upper surfaces of the second electrode film and the second insulating film; forming an overhung portion on the second electrode film so as to overhang on the insulating film by performing a selective growth process; and forming a low resistance layer at the overhung portion and the second electrode film by performing an alloying process.

摘要翻译： 根据本发明的一个方面，提供了一种用于制造半导体器件的方法，包括：在衬底上依次形成第一绝缘膜，第一电极膜，第二绝缘膜和第二电极膜; 形成分隔第二电极膜，第二绝缘膜和第一电极膜的槽; 在所述槽内形成绝缘膜，使得其上表面位于所述第二电极膜的上表面和所述第二绝缘膜之间; 在所述第二电极膜上形成悬垂部分，以通过进行选择性生长工艺在绝缘膜上悬垂; 以及通过进行合金化处理在所述悬臂部分和所述第二电极膜上形成低电阻层。