公开(公告)号：US07181835B2

公开(公告)日：2007-02-27

申请号：US10759989

申请日：2004-01-15

申请人： Ah Lek Hu ,  Sharon Mei Wan Ko ,  Peng Yeen Chan ,  Jaime Bayan

发明人： Ah Lek Hu ,  Sharon Mei Wan Ko ,  Peng Yeen Chan ,  Jaime Bayan

IPC分类号： H05K3/30

CPC分类号： H01L21/6835 ,  H01L21/67144 ,  H01L21/6838 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/53174 ,  Y10T29/53191

摘要： A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface of the porous block. A device for processing lead frames comprises a porous block with a first side and a second side, and a vacuum system connected to the first side of the porous block. The device may also include devices for attaching chips to the lead frame and wire bonding the chips to the lead frame.

摘要翻译： 提供了一种用于处理引线框架的方法。 通常，引线框架基带的第一表面被放置在引线框架的第一表面上。 引线框架基带的第二表面放置在多孔块的第一表面上。 在多孔块的第二表面上放置真空。 用于处理引线框架的装置包括具有第一侧和第二侧的多孔块，以及连接到多孔块的第一侧的真空系统。 该装置还可以包括用于将芯片附接到引线框架并将芯片引线接合到引线框架的装置。

公开(公告)号：US06698088B2

公开(公告)日：2004-03-02

申请号：US09776287

申请日：2001-02-01

申请人： Ah Lek Hu ,  Sharon Mei Wan Ko ,  Peng Yeen Chan ,  Jaime Bayan

发明人： Ah Lek Hu ,  Sharon Mei Wan Ko ,  Peng Yeen Chan ,  Jaime Bayan

IPC分类号： B23P1900

CPC分类号： H01L21/6835 ,  H01L21/67144 ,  H01L21/6838 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/53174 ,  Y10T29/53191

摘要： A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface of the porous block. A device for processing lead frames comprises a porous block with a first side and a second side, and a vacuum system connected to the first side of the porous block. The device may also include devices for attaching chips to the lead frame and wire bonding the chips to the lead frame.

摘要翻译： 提供了一种用于处理引线框架的方法。 通常，引线框架基带的第一表面被放置在引线框架的第一表面上。 引线框架基带的第二表面放置在多孔块的第一表面上。 在多孔块的第二表面上放置真空。 用于处理引线框架的装置包括具有第一侧和第二侧的多孔块，以及连接到多孔块的第一侧的真空系统。 该装置还可以包括用于将芯片附接到引线框架并将芯片引线接合到引线框架的装置。

公开(公告)号：US06399415B1

公开(公告)日：2002-06-04

申请号：US09528658

申请日：2000-03-20

申请人： Jaime Bayan ,  Peter Howard Spalding ,  Harry Cheng Hong Kam ,  Ah Lek Hu ,  Sharon Mei Wan Ko ,  Santhiran Nadarajah ,  Aik Seng Kang ,  Yin Yen Bong

发明人： Jaime Bayan ,  Peter Howard Spalding ,  Harry Cheng Hong Kam ,  Ah Lek Hu ,  Sharon Mei Wan Ko ,  Santhiran Nadarajah ,  Aik Seng Kang ,  Yin Yen Bong

IPC分类号： H01L2144

CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/8547 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A variety of techniques for electrically debussing conductive substrate panels used in the formation of a matrix of leadless integrated circuit packages are described. Generally, after a matrix of leadless packages have been fabricated in panel form on a conductive substrate panel, tie bars that are used to support contacts and potentially other structures on the conductive substrate are removed after plastic caps have been molded over the matrix, but before separating the packaged devices. This serves to electrically isolate the contacts from one another while leaving sufficient portions of the molded substrate structure in tact to facilitate handling the structure in panel form. With the described arrangement, the packaged devices may be tested in panel form. After testing and any other desired panel based operations, the packaged devices may be separated using conventional techniques. The removal of the tie bars can be accomplished by any suitable technique including, for example, sawing or etching.

摘要翻译： 描述了用于形成无引线集成电路封装的矩阵的导电基板面板的各种技术。 通常，在导电基板面板上以面板形式制造无引线封装的矩阵之后，在塑料盖已经在基体上模塑之后，但是在导电基板上模制了用于支撑触点和导电基板上潜在的其它结构的连接杆 分离包装的设备。 这用于将触头彼此电隔离，同时留下模制基板结构的足够部分以便于以面板形式处理结构。 利用所述的布置，封装的装置可以以面板形式进行测试。 在测试和任何其它期望的基于面板的操作之后，可以使用常规技术来分离封装的装置。 拉杆的移除可以通过任何合适的技术来实现，包括例如锯切或蚀刻。

公开(公告)号：US06452255B1

公开(公告)日：2002-09-17

申请号：US09528662

申请日：2000-03-20

申请人： Jaime Bayan ,  Peter Howard Spalding ,  Harry Cheng Hong Kam ,  Ah Lek Hu ,  Sharon Mei Wan Ko ,  Santhiran Nadarajah ,  Aik Seng Kang ,  Yin Yen Bong

发明人： Jaime Bayan ,  Peter Howard Spalding ,  Harry Cheng Hong Kam ,  Ah Lek Hu ,  Sharon Mei Wan Ko ,  Santhiran Nadarajah ,  Aik Seng Kang ,  Yin Yen Bong

IPC分类号： H01L23495

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/4554

摘要： A variety of leadless packaging arrangements and methods of packaging integrated circuits in leadless packages that are arranged to have relatively low inductance are disclosed. In one aspect, a leadless semiconductor package is described having an exposed die pad and a plurality of exposed contacts that are formed from a common substrate material. The die attach pad, however, is thinned relative to at least a portion of the contacts. A die is mounted on the thinned die attach pad and wire bonded to the contacts. Since the die attach pad is lower than the contact surface being wire bonded to, the length of the bonding wires can be relatively reduced, thereby reducing inductance of the device. A plastic cap is molded over the die and the contacts thereby encapsulating the bonding wires while leaving the bottom surface of the contacts exposed. In some embodiments, the die is arranged to overhangs beyond the die attach pad towards the contacts. In other embodiments, a portion of at least some of the contacts are thinned to a thickness substantially similar to the die attach pad to form contact shelves. The die is then mounted such that it bridges the die attach pad to the contact shelves. In some of the embodiments, reverse wire bonding is used to further shorten the bonding wires. The described devices are packaged in bulk on a conductive substrate panel.

摘要翻译： 公开了各种无引线封装结构和封装集成电路的无引线封装的方法，其被布置为具有相对低的电感。 一方面，描述了一种无引线半导体封装，其具有暴露的管芯焊盘和由公共衬底材料形成的多个暴露的触点。 然而，芯片附接垫相对于至少一部分触点变薄。 模具安装在减薄的芯片附着焊盘上，并且焊接到触点上。 由于管芯安装焊盘低于被接合的接触面，所以可以相对地减小接合线的长度，从而降低设备的电感。 在模具上模制塑料盖，并且触头由此封装接合线，同时使触点的底表面露出。 在一些实施例中，管芯被设置成超过管芯附接垫朝向接触件突出。 在其他实施例中，至少一些触头的一部分被薄化到基本上类似于管芯附接垫的厚度以形成接触架。 然后将模具安装成使得其将管芯附接垫桥接到接触架上。 在一些实施例中，使用反向引线接合来进一步缩短接合线。 所描述的器件在体积封装在导电衬底面板上。

公开(公告)号：US06686652B1

公开(公告)日：2004-02-03

申请号：US09616228

申请日：2000-07-14

申请人： Jaime Bayan ,  Peter H. Spalding ,  Harry Cheng-Hong Kam ,  Ah Lek Hu ,  Sharon Mei Wan Ko ,  Santhiran Nadarajah ,  Aik Seng Kang ,  Yin Yen Bong

发明人： Jaime Bayan ,  Peter H. Spalding ,  Harry Cheng-Hong Kam ,  Ah Lek Hu ,  Sharon Mei Wan Ko ,  Santhiran Nadarajah ,  Aik Seng Kang ,  Yin Yen Bong

IPC分类号： H01L2302

CPC分类号： H01L23/49548 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： An assembly and method suitable for use in packaging integrated circuits including a support substrate for supporting an integrated circuit die embedded in a molded encapsulating cap. The substrate includes a conductive die attach pad adapted to be molded into the encapsulating cap. The pad includes an interior facing support surface and a spaced-apart exterior facing exposed surface defined by a peripheral edge. The support surface is adapted to support the embedded die, while the exposed surface is to be exposed from the encapsulating cap. The attach pad further includes a locking ledge portion extending outward peripherally beyond at least a portion of the exposed surface peripheral edge. This ledge is adapted to be subtended in the encapsulating cap in a manner substantially preventing a pull-out of the attach pad in a direction away from the encapsulating cap.

摘要翻译： 一种适用于封装集成电路的组件和方法，该集成电路包括用于支撑嵌入在模制封装盖中的集成电路芯片的支撑衬底。 衬底包括适于模制到封装盖中的导电管芯附接垫。 垫包括面向内部的支撑表面和由外围边缘限定的间隔开的面向外部的表面。 支撑表面适于支撑嵌入的模具，同时露出的表面将从封装盖露出。 附接垫还包括锁定凸缘部分，该凸缘部分在周边外延伸超出暴露的表面周边边缘的至少一部分。 该凸缘适于以基本上防止附着垫在远离密封盖的方向拉出的方式对着封装盖中。

公开(公告)号：US07102209B1

公开(公告)日：2006-09-05

申请号：US10650325

申请日：2003-08-27

申请人： Jaime Bayan ,  Ashok S. Prabhu ,  Fred Drummond

发明人： Jaime Bayan ,  Ashok S. Prabhu ,  Fred Drummond

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A lead-frame based substrate panel for use in semiconductor packaging is described. The substrate panel includes a lead-frame panel having at least one array of device areas. Each device area has a plurality of contacts. The lead-frame panel is filled with a dielectric material to form a relatively rigid substrate panel that can be used for packaging integrated circuits. The top surface of the dielectric material is typically substantially coplanar with the top surface of the lead-frame panel, and the bottom surface of the dielectric material is typically substantially coplanar with the bottom surface of the lead-frame panel.

摘要翻译： 描述了用于半导体封装的基于引线框架的基板面板。 衬底面板包括具有至少一个器件区域阵列的引线框架面板。 每个设备区域具有多个触点。 引线框板填充有电介质材料以形成可用于封装集成电路的相对刚性的基板。 电介质材料的顶表面通常与引线框架板的顶表面基本上共面，并且电介质材料的底表面通常与引线框架板的底表面基本上共面。

公开(公告)号：US06963124B1

公开(公告)日：2005-11-08

申请号：US10943476

申请日：2004-09-17

申请人： Harry Kam Cheng Hong ,  Hu Ah Lek ,  Santhiran Nadarajah ,  Sharon Ko Mei Wan ,  Chan Peng Yeen ,  Jaime Bayan ,  Peter Howard Spalding

发明人： Harry Kam Cheng Hong ,  Hu Ah Lek ,  Santhiran Nadarajah ,  Sharon Ko Mei Wan ,  Chan Peng Yeen ,  Jaime Bayan ,  Peter Howard Spalding

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L23/3121 ,  H01L23/3142 ,  H01L23/49548 ,  H01L24/97 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： A panel assembly of packaged integrated circuit devices including a conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.

摘要翻译： 一种封装集成电路器件的面板组件，包括具有一组器件区域的导电衬底面板和多个锁定通道。 锁定通道围绕围绕装置区域阵列的周边的非活动缓冲区域定位。 面板组件还包括模制顶盖，其模制在面板的顶部以封装装置区域阵列和非活动缓冲区域。 模制帽包括符合锁定杆部分，其以将模制帽锁定到衬底面板的方式延伸到每个锁定通道中，使得在单元化设备区域期间，模制帽不会在非活动缓冲器处与衬底面板分离 区。 在本发明的另一方面，描述了一种用于制造具有锁定通道的面板组件的方法。

公开(公告)号：US06576989B1

公开(公告)日：2003-06-10

申请号：US09724727

申请日：2000-11-28

申请人： Harry Kam Cheng Hong ,  Hu Ah Lek ,  Santhiran Nadarajah ,  Sharon Ko Mei Wan ,  Chan Peng Yeen ,  Jaime Bayan ,  Peter Howard Spalding

发明人： Harry Kam Cheng Hong ,  Hu Ah Lek ,  Santhiran Nadarajah ,  Sharon Ko Mei Wan ,  Chan Peng Yeen ,  Jaime Bayan ,  Peter Howard Spalding

IPC分类号： H01L2302

CPC分类号： H01L23/13 ,  H01L23/3121 ,  H01L24/97 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： A panel assembly of packaged integrated circuit devices including conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The locking passageways extend from a topside of the panel toward a bottom side of the panel. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described. The method involves providing a conductive substrate panel having the locking passageways and applying molding material to the topside of the substrate panel such that the solidified molding material forms stems that conform to the passageways.

摘要翻译： 一种封装集成电路器件的面板组件，包括具有一组器件区域和多个锁定通道的导电衬底面板。 锁定通道围绕围绕装置区域阵列的周边的非活动缓冲区域定位。 锁定通道从面板的顶部朝向面板的底侧延伸。 面板组件还包括模制顶盖，其模制在面板的顶部以封装装置区域阵列和非活动缓冲区域。 模制帽包括符合锁定杆部分，其以将模制帽锁定到衬底面板的方式延伸到每个锁定通道中，使得在单元化设备区域期间，模制帽不会在非活动缓冲器处与衬底面板分离 区。 在本发明的另一方面，描述了一种用于制造具有锁定通道的面板组件的方法。 该方法包括提供具有锁定通道的导电基板面板，并将模塑材料施加到基板面板的顶侧，使得固化的模制材料形成符合通道的阀杆。

公开(公告)号：US08375577B2

公开(公告)日：2013-02-19

申请号：US12133335

申请日：2008-06-04

申请人： Will Wong ,  Nghia Thuc Tu ,  Jaime Bayan ,  David Chin

发明人： Will Wong ,  Nghia Thuc Tu ,  Jaime Bayan ,  David Chin

IPC分类号： H01L21/60 ,  H01L23/495

CPC分类号： H01L23/49582 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/544 ,  H01L24/29 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49146 ,  Y10T29/49156 ,  Y10T428/12438 ,  H01L2224/85 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/83205 ,  H01L2924/00012

摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages. Some embodiments relate to methods that utilize some or all of the aforementioned operations. Other embodiments relate to arrangements used in the above processes.

摘要翻译： 本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。 在一个实施例中，通过将导电箔的部分超声波结合到金属载体上来形成箔载体结构。 接合部分限定箔载体结构中的面板。 在一些实施例中，切割箔载体结构以形成沿其周边密封的多个隔离板。 每个隔离的面板可以是常规引线框条或面板的尺寸。 因此，可以使用现有的包装设备将骰子，接合线和模制材料添加到面板。 超声波焊接有助于防止在这种加工步骤期间不需要的物质渗透到箔片载体结构。 在模制的箔载体结构的载体部分被去除之后，将结构分成集成电路封装。 一些实施例涉及利用上述操作中的一些或全部的方法。 其他实施例涉及上述方法中使用的布置。

公开(公告)号：US08101470B2

公开(公告)日：2012-01-24

申请号：US12571202

申请日：2009-09-30

申请人： Anindya Poddar ,  Nghia Thuc Tu ,  Jaime Bayan ,  Will Wong ,  David Chin

发明人： Anindya Poddar ,  Nghia Thuc Tu ,  Jaime Bayan ,  Will Wong ,  David Chin

IPC分类号： H01L23/28 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/568 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2924/00

摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.

摘要翻译： 本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。 本发明的一个实施例涉及将多个骰子附接到箔片载体结构。 箔载体结构由结合到载体的薄箔制成。 然后将模具和至少一部分金属箔用模制材料包封。 移除载体，留下模制的箔结构。 使用光刻技术对暴露的箔进行图案化和蚀刻，以在箔中限定多个器件区域。 每个设备区域包括多条导线。 之后，导电线的一部分被电介质材料覆盖，并且其它部分被暴露以在器件区域中限定多个接合焊盘。 模制的箔结构可以被单个化以形成多个集成电路封装。