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    Foil based semiconductor package
    1.
    发明授权
    Foil based semiconductor package 有权
    箔基半导体封装

    公开(公告)号：US08101470B2

    公开(公告)日：2012-01-24

    申请号：US12571202

    申请日：2009-09-30

    申请人： Anindya Poddar ,  Nghia Thuc Tu ,  Jaime Bayan ,  Will Wong ,  David Chin

    发明人： Anindya Poddar ,  Nghia Thuc Tu ,  Jaime Bayan ,  Will Wong ,  David Chin

    IPC分类号： H01L23/28 ,  H01L21/56

    CPC分类号： H01L23/3107 ,  H01L21/568 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2924/00

    摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.

    摘要翻译： 本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。 本发明的一个实施例涉及将多个骰子附接到箔片载体结构。 箔载体结构由结合到载体的薄箔制成。 然后将模具和至少一部分金属箔用模制材料包封。 移除载体，留下模制的箔结构。 使用光刻技术对暴露的箔进行图案化和蚀刻，以在箔中限定多个器件区域。 每个设备区域包括多条导线。 之后，导电线的一部分被电介质材料覆盖，并且其它部分被暴露以在器件区域中限定多个接合焊盘。 模制的箔结构可以被单个化以形成多个集成电路封装。

    Inkjet printed leadframe
    4.
    发明授权
    Inkjet printed leadframe 有权
    喷墨印刷引线框

    公开(公告)号：US07824963B2

    公开(公告)日：2010-11-02

    申请号：US12626440

    申请日：2009-11-25

    申请人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

    发明人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

    IPC分类号： H01L21/44 ,  H01L23/495

    CPC分类号： H01L21/4821 ,  H01L21/6835 ,  H01L23/49579 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2924/14 ,  H01L2924/00

    摘要： Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.

    摘要翻译： 公开了用于集成电路装置的用于喷墨印刷电互连图案的引线框架的装置和方法。 一种用于包装的装置包括适于高温处理的薄基板，以及使用金属纳米接头喷墨印刷到薄基板上的连接焊盘和接触区域。 然后将nanoink固化以除去液体内容物。 剩余的金属引线框架或电互连图案具有约10至50微米或更小的基本一致的厚度。 相关联的面板组件包括导电衬底面板，该导电衬底面板具有多个单独的器件阵列，每个单独的器件阵列包括多个电互连图案，每个均包括安装在导电衬底面板上的多个集成电路器件，以及封装集成电路器件和相关联的电互连图案的模制帽。 模制帽在每个分离的装置阵列上具有基本均匀的厚度，并且延伸到分离的装置阵列之间的空间中。

    Method of packaging integrated circuits
    5.
    发明授权
    Method of packaging integrated circuits 有权
    集成电路封装方法

    公开(公告)号：US07612435B2

    公开(公告)日：2009-11-03

    申请号：US11963388

    申请日：2007-12-21

    申请人： Jaime A. Bayan ,  Anindya Poddar

    发明人： Jaime A. Bayan ,  Anindya Poddar

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49548 ,  H01L23/3185 ,  H01L23/49537 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/09701 ,  H01L2924/19041

    摘要： A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead.

    摘要翻译： 描述了一种封装具有多个I / O焊盘的集成电路管芯的方法。 该方法包括将管芯定位在包括多个第一引线的第一引线框的管芯附着区域内。 该方法还包括在第一引线框上定位包括多个第二引线的第二引线框架。 该方法还包括将每个第二引线电连接到相关联的I / O焊盘和第一引线。

    Spacer with passive components for use in multi-chip modules
    8.
    发明授权
    Spacer with passive components for use in multi-chip modules 有权
    带无源元件的隔板用于多芯片模块

    公开(公告)号：US06933597B1

    公开(公告)日：2005-08-23

    申请号：US10192173

    申请日：2002-07-09

    申请人： Anindya Poddar ,  Ashok S. Prabhu

    发明人： Anindya Poddar ,  Ashok S. Prabhu

    IPC分类号： H01L23/02 ,  H01L23/552 ,  H01L25/065

    CPC分类号： H01L25/0657 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A method for providing passive circuit functions in a multi-chip module and the multi-chip modules that result from incorporating these function is disclosed. Passive components such as resistors, capacitors and inductors are fabricated on or within a non-conductive spacer. The spacer is then placed between two active semiconductor dies and coupled electrically to either one or both of the dies. In this manner, area of the active dies that would normally have to be used for such passive components is freed for other uses and the spacer, which was already required in multi-chip modules, is endowed with extra functionality. In another embodiment, one or both surfaces of the spacer are coated with a conductive metal and the passive components are located within the spacer. In this embodiment, the spacer provides electromagnetic interference protection between the active dies.

    摘要翻译： 公开了一种在多芯片模块中提供无源电路功能的方法以及由这些功能引入的多芯片模块。 诸如电阻器，电容器和电感器的无源部件制造在非导电间隔件上或内部。 然后将间隔物放置在两个有源半导体管芯之间，并且电连接到裸片之一或两者。 以这种方式，通常必须用于这种无源部件的有源管芯的面积被释放用于其他用途，并且已经在多芯片模块中已经需要的间隔件具有额外的功能。 在另一个实施例中，间隔物的一个或两个表面涂覆有导电金属，并且无源部件位于间隔物内。 在该实施例中，间隔件在活动管芯之间提供电磁干扰保护。

    Integrated circuit package having offset segmentation of package power and/or ground planes and methods for reducing delamination in integrated circuit packages
    9.
    发明授权
    Integrated circuit package having offset segmentation of package power and/or ground planes and methods for reducing delamination in integrated circuit packages 有权
    具有封装功率和/或接地层的偏移分割的集成电路封装以及用于减少集成电路封装中的分层的方法

    公开(公告)号：US06465890B1

    公开(公告)日：2002-10-15

    申请号：US09724610

    申请日：2000-11-28

    申请人： Anindya Poddar ,  Ka Heng The

    发明人： Anindya Poddar ,  Ka Heng The

    IPC分类号： H01L2348

    CPC分类号： H01L23/5286 ,  H01L2224/48227

    摘要： Integrated circuit packages having offset segmentation, or splitting, of package power and/or ground layers and methods for preventing delamination in package substrates having segmented power and/or ground layers are described. The package substrate includes a plurality of split power and/or ground plane layers that are isolated by split lines. The split lines from at least two of the split power and/or ground plane layers are offset relative to one another. In some embodiments, in addition to being offset, the split lines may be arranged to minimize their respective cross-over points, as well as convoluted to increase their effective length.

    摘要翻译： 描述了具有封装功率和/或接地层的偏移分割或分离的集成电路封装以及用于防止具有分段功率和/或接地层的封装衬底中的分层的方法。 封装衬底包括被分割线隔离的多个分裂电源和/或接地平面层。 来自分裂功率和/或接地平面层中的至少两个的分裂线相对于彼此偏移。 在一些实施例中，除了被偏移之外，分割线可以被布置成使其相应的交叉点最小化，以及被卷绕以增加其有效长度。