公开(公告)号：US08346992B2

公开(公告)日：2013-01-01

申请号：US13111673

申请日：2011-05-19

申请人： Ajai K. Singh ,  David Puffer

发明人： Ajai K. Singh ,  David Puffer

IPC分类号： G06F3/00

CPC分类号： G06F11/0766 ,  G06F11/085 ,  H04L41/06

摘要： According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

摘要翻译： 根据一些实施例，在上游设备处接收由下游设备生成的消息。 消息可以例如经由外设接口被接收并且可能不需要响应。 然后可以确定错误与消息相关联，并且警报消息可以经由外围接口从上游设备发送到下游设备。

公开(公告)号：US20110225469A1

公开(公告)日：2011-09-15

申请号：US13111673

申请日：2011-05-19

申请人： Ajai K. Singh ,  David Puffer

发明人： Ajai K. Singh ,  David Puffer

IPC分类号： G06F11/07

CPC分类号： G06F11/0766 ,  G06F11/085 ,  H04L41/06

摘要： According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

摘要翻译： 根据一些实施例，在上游设备处接收由下游设备生成的消息。 消息可以例如经由外设接口被接收并且可能不需要响应。 然后可以确定错误与消息相关联，并且警报消息可以经由外围接口从上游设备发送到下游设备。

公开(公告)号：US07970958B2

公开(公告)日：2011-06-28

申请号：US11156838

申请日：2005-06-20

申请人： Ajai K. Singh ,  David Puffer

发明人： Ajai K. Singh ,  David Puffer

IPC分类号： G06F3/00 ,  G06F11/00

CPC分类号： G06F11/0766 ,  G06F11/085 ,  H04L41/06

摘要： According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

摘要翻译： 根据一些实施例，在上游设备处接收由下游设备生成的消息。 消息可以例如经由外设接口被接收并且可能不需要响应。 然后可以确定错误与消息相关联，并且警报消息可以经由外围接口从上游设备发送到下游设备。

公开(公告)号：US20150169439A1

公开(公告)日：2015-06-18

申请号：US14133097

申请日：2013-12-18

申请人： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

发明人： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/126

摘要： A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

摘要翻译： 处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。 钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。 钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。 此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中 并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。

公开(公告)号：US11768781B2

公开(公告)日：2023-09-26

申请号：US17827556

申请日：2022-05-27

申请人： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

发明人： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC分类号： G06F9/455 ,  G06F9/50 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

CPC分类号： G06F13/16 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/4068 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/60 ,  G06F2212/68

摘要： An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US07120765B2

公开(公告)日：2006-10-10

申请号：US10284596

申请日：2002-10-30

申请人： James M. Dodd ,  David Puffer

发明人： James M. Dodd ,  David Puffer

IPC分类号： G06F12/00

CPC分类号： G06F13/1626

摘要： Machine-readable media, methods, and apparatus are described which order memory transactions to increase utilization of multiple memory channels. In some embodiments, a processor may determine an issue order for memory transactions based on the memory channels that are to service the memory transactions. In some embodiments, the processor attempts to obtain an issue order that minimizes or reduces the number of idle periods experienced by the memory channels. Further, the processor may issue the memory transactions to an external memory controller for servicing in the determined issue order.

摘要翻译： 描述了命令存储器事务以增加多个存储器通道的利用率的机器可读介质，方法和装置。 在一些实施例中，处理器可以基于要对存储器事务进行服务的存储器通道来确定存储器事务的发布顺序。 在一些实施例中，处理器尝试获得使存储器通道经历的空闲周期数量最小化或减少的问题顺序。 此外，处理器可以将存储器事务发布到外部存储器控制器，以按照确定的发布顺序进行维修。

公开(公告)号：US20220269433A1

公开(公告)日：2022-08-25

申请号：US17682015

申请日：2022-02-28

申请人： Rahul Pal ,  Susanne M. Balle ,  David Puffer ,  Nagabhushan Chitlur

发明人： Rahul Pal ,  Susanne M. Balle ,  David Puffer ,  Nagabhushan Chitlur

IPC分类号： G06F3/06

摘要： In an embodiment, an apparatus includes: a first downstream port to couple to a first peer device; a second downstream port to couple to a second peer device; and a peer-to-peer (PTP) circuit to receive a memory access request from the first peer device, the memory access request having a target associated with the second peer device, where the PTP circuit is to convert the memory access request from a coherent protocol to a memory protocol and send the converted memory access request to the second peer device. Other embodiments are described and claimed.

公开(公告)号：US20210042254A1

公开(公告)日：2021-02-11

申请号：US17083200

申请日：2020-10-28

申请人： Pratik Marolia ,  Andrew Herdrich ,  Rajesh Sankaran ,  Rahul Pal ,  David Puffer ,  Sayantan Sur ,  Ajaya Durg

发明人： Pratik Marolia ,  Andrew Herdrich ,  Rajesh Sankaran ,  Rahul Pal ,  David Puffer ,  Sayantan Sur ,  Ajaya Durg

IPC分类号： G06F13/40 ,  G06F13/42

摘要： Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

公开(公告)号：US20190303334A1

公开(公告)日：2019-10-03

申请号：US16447025

申请日：2019-06-20

申请人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

发明人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06T1/20

摘要： In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

公开(公告)号：US20180285106A1

公开(公告)日：2018-10-04

申请号：US15477033

申请日：2017-04-01

申请人： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kamal Sinha ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  David Puffer ,  Supratim Pal ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

发明人： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kamal Sinha ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  David Puffer ,  Supratim Pal ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC分类号： G06F9/30 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/46 ,  G09G5/36

摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.