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431 条记录 (耗时 0.025 秒)

    Method of releasing devices from a substrate
    1.
    发明授权
    Method of releasing devices from a substrate 失效
    从基板释放装置的方法

    公开(公告)号：US06905616B2

    公开(公告)日：2005-06-14

    申请号：US10382562

    申请日：2003-03-05

    申请人： Ajay Kumar ,  Anisul H Khan ,  Sanjay M Thekdi ,  Sharma V Pamarthy

    发明人： Ajay Kumar ,  Anisul H Khan ,  Sanjay M Thekdi ,  Sharma V Pamarthy

    IPC分类号： B31D3/00 ,  B44C1/22 ,  B81C1/00 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/00

    CPC分类号： B81C1/00952

    摘要： Micro devices are formed in situ in a high density in a substrate comprising a masked silicon layer over a stop layer of a silicon compound, by anisotropically etching the desired feature in the silicon layer, overetching to form a notch at the silicon-stop layer interface, depositing a protective fluorocarbon polymer layer on the sidewalls and bottom of the etched silicon layer, and isotropically etching to separate the etched feature from the stop layer. This method avoids the problems of stiction common in other methods of forming micro devices.

    摘要翻译： 通过各向异性地蚀刻硅层中的所需特征，在基底上形成微孔器件，在衬底上形成掩模硅层，通过各向异性蚀刻硅层中的所需特征，过蚀刻以在硅 - 停止层界面处形成缺口 ，在蚀刻硅层的侧壁和底部上沉积保护性碳氟聚合物层，并进行各向同性蚀刻以将蚀刻的特征与停止层分离。 这种方法避免了在其他形成微器件的方法中常见的静电问题。

    Method for etching high-aspect-ratio features
    2.
    发明授权
    Method for etching high-aspect-ratio features 失效
    蚀刻高纵横比特征的方法

    公开(公告)号：US06897155B2

    公开(公告)日：2005-05-24

    申请号：US10219885

    申请日：2002-08-14

    申请人： Ajay Kumar ,  Anisul H. Khan ,  Dragan Podlesnik ,  Sharma V. Pamarthy ,  Axel Henke ,  Stephan Wege ,  Virinder Grewal

    发明人： Ajay Kumar ,  Anisul H. Khan ,  Dragan Podlesnik ,  Sharma V. Pamarthy ,  Axel Henke ,  Stephan Wege ,  Virinder Grewal

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/461

    CPC分类号： H01J37/32082 ,  H01J2237/3347 ,  H01L21/3065 ,  H01L21/30655

    摘要： A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.

    摘要翻译： 一种用于操作等离子体反应器以蚀刻真空室中的工件上的高纵横比特征的方法。 该方法包括执行闪光处理之后的蚀刻工艺。 在蚀刻工艺期间，将第一气体供应到真空室中，并且第一气体的等离子体保持第一时间段。 第一气体的等离子体包括蚀刻剂和钝化物质。 在闪蒸过程中，将包含沉积物去除气体的第二气体供应到真空室中，并且将第二气体的等离子体保持第二时间段。 在第二时间段期间，工件与第二气体的等离子体之间的直流电压明显小于在第一时间段内第一气体的工件和等离子体之间的直流电压。

    Etching multi-shaped openings in silicon
    6.
    发明授权
    Etching multi-shaped openings in silicon 失效
    在硅中蚀刻多形开口

    公开(公告)号：US06979652B2

    公开(公告)日：2005-12-27

    申请号：US10118763

    申请日：2002-04-08

    申请人： Anisul Khan ,  Sharma V Pamarthy ,  Sanjay Thekdi ,  Ajay Kumar

    发明人： Anisul Khan ,  Sharma V Pamarthy ,  Sanjay Thekdi ,  Ajay Kumar

    IPC分类号： C23F1/00 ,  H01L21/302 ,  H01L21/3065

    CPC分类号： H01L21/30655

    摘要： Openings of variable shape are made sequentially by alternately etching an opening in silicon and depositing a conformal fluorocarbon polymer on the sidewalls. This polymer protects the sidewalls of the opening from further etching. An isotropic etch can be carried out to change the profile of the etched feature, and for lift-off of the etched feature from the silicon substrate.

    摘要翻译： 通过交替蚀刻硅中的开口并在侧壁上沉积共形氟碳聚合物来顺序地制备可变形状的开口。 该聚合物保护开口的侧壁进一步蚀刻。 可以进行各向同性蚀刻以改变蚀刻特征的轮廓，并且用于从硅衬底剥离蚀刻的特征。

    Method of etching a trench in a silicon-on-insulator (SOI) structure
    7.
    发明授权
    Method of etching a trench in a silicon-on-insulator (SOI) structure 失效
    蚀刻绝缘体上硅（SOI）结构中的沟槽的方法

    公开(公告)号：US06759340B2

    公开(公告)日：2004-07-06

    申请号：US10143269

    申请日：2002-05-09

    申请人： Padmapani C. Nallan ,  Ajay Kumar ,  Anisul H. Khan ,  Chan-Syun David Yang

    发明人： Padmapani C. Nallan ,  Ajay Kumar ,  Anisul H. Khan ,  Chan-Syun David Yang

    IPC分类号： H01L21302

    CPC分类号： H01L21/30655

    摘要： Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.

    摘要翻译： 本文公开了一种在覆盖电介质材料的硅中蚀刻沟槽的方法，其减小或基本上消除在沟槽的基部处的凹口，同时减少沟槽侧壁上的扇形。 该方法包括通过将硅衬底通过图案化掩模层暴露于由含氟气体产生的等离子体来蚀刻沟槽的第一部分。 该蚀刻之后是聚合物沉积步骤，包括将衬底暴露于由能够在蚀刻的硅表面上形成聚合物的气体产生的等离子体。 根据沟槽第一部分的期望深度，蚀刻和聚合物沉积步骤重复多个循环。 通过将硅暴露于由含氟气体和聚合物形成气体的组合产生的等离子体来蚀刻沟槽的最后部分。