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    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07045864B2

    公开(公告)日：2006-05-16

    申请号：US10170432

    申请日：2002-06-14

    申请人： Kota Funayama ,  Yasuko Yoshida ,  Masaru Nakamichi ,  Akio Nishida

    发明人： Kota Funayama ,  Yasuko Yoshida ,  Masaru Nakamichi ,  Akio Nishida

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/092 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： A semiconductor integrated circuit device, e.g., a memory cell of an SRAM, is formed of a pair of inverters having their input and output points connected in a crisscross manner and being formed of drive n-channel MISFETs and load p-channel MISFETs. The n-channel MISFETs and p-channel MISFETs have their back gates supplied with power supply voltage and a ground voltage, respectively. The MISFETs are formed with a metal silicide layer on the gate electrodes G and source regions (hatched areas) and without the formation of a metal silicide layer on the drain regions, respectively, whereby the leakage current of the MISFETs due to a voltage difference between the drain regions and wells can be reduced, and, thus, the power consumption can be reduced.

    摘要翻译： 诸如SRAM的存储单元的半导体集成电路器件由一对反相器形成，它们的输入和输出点以十字交叉的方式连接并且由驱动n沟道MISFET和负载p沟道MISFET形成。 n沟道MISFET和p沟道MISFET分别具有电源电压和接地电压的后门。 MISFET在栅极电极G和源极区域（阴影区域）上形成有金属硅化物层，并且在漏极区域上不形成金属硅化物层，由此由于MISFET的漏电流由于 可以减少漏区和阱，从而可以降低功耗。

    Manufacturing method of semiconductor device
    2.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US07666728B2

    公开(公告)日：2010-02-23

    申请号：US12028593

    申请日：2008-02-08

    申请人： Shuji Matsuo ,  Katsuhiro Uchimura ,  Yasuko Yoshida ,  Kota Funayama ,  Yutaka Takeshima

    发明人： Shuji Matsuo ,  Katsuhiro Uchimura ,  Yasuko Yoshida ,  Kota Funayama ,  Yutaka Takeshima

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/302

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

    摘要： A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

    摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成栅极绝缘膜和由多晶硅制成的栅电极; 将离子注入到半导体衬底中以形成作为源极或漏极的半导体区域; 在所述半导体衬底上形成钴膜和氮化钛膜以覆盖所述栅电极; 进行退火以引起Co和Si之间的反应以及半导体区域以形成CoSi层; 进行湿式清洗以除去氮化钛膜和未反应的钴膜，使CoSi层离开栅电极和半导体区域; 进行退火以引起CoSi层与栅极电极和半导体区域之间的反应以形成CoSi 2层; 进行HPM清洗; 以及通过低压CVD在半导体衬底上形成氮化硅膜以覆盖栅电极。

    Manufacturing method of semiconductor device
    3.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US07348230B2

    公开(公告)日：2008-03-25

    申请号：US11008276

    申请日：2004-12-10

    申请人： Shuji Matsuo ,  Katsuhiro Uchimura ,  Yasuko Yoshida ,  Kota Funayama ,  Yutaka Takeshima

    发明人： Shuji Matsuo ,  Katsuhiro Uchimura ,  Yasuko Yoshida ,  Kota Funayama ,  Yutaka Takeshima

    IPC分类号： H01L21/336

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

    摘要： A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成栅极绝缘膜和由多晶硅制成的栅电极; 将离子注入到半导体衬底中以形成作为源极或漏极的半导体区域; 在所述半导体衬底上形成钴膜和氮化钛膜以覆盖所述栅电极; 进行退火以引起Co和Si之间的反应以及半导体区域以形成CoSi层; 进行湿式清洗以除去氮化钛膜和未反应的钴膜，使CoSi层离开栅极电极和半导体区域; 进行退火以引起CoSi层和栅极电极和半导体区域之间的反应以形成CoSi 2 O 3层; 进行HPM清洗; 以及通过低压CVD在半导体衬底上形成氮化硅膜以覆盖栅电极。

    Method for manufacturing semiconductor device
    4.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06403446B1

    公开(公告)日：2002-06-11

    申请号：US09536447

    申请日：2000-03-28

    申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

    发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

    IPC分类号： H01L2176

    CPC分类号： H01L21/76232 ,  Y10S148/05

    摘要： Manufacturing a semiconductor device avoiding an increase of transistor leak current or reduction of the withstanding voltage characteristics is by at least one of: The pad oxide film is removed along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm: The exposed surface of the semiconductor substrate undergoes removal by isotropic etching within 20 nm; and oxidizing a groove portion formed in a semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H2) to oxygen (O2) being less than or equal to 0.5, an increase of the curvature radius beyond 3nm is achieved without associating the risk of creation of any level difference on the substrate surface at or near the upper groove edge portions in a groove separation structure. This eliminates either an increase of transistor leak current or reduction of the withstanding voltage characteristics thereof otherwise occurring due to local electric field concentration near or around the terminate ends of a gate electrode film which in turn leads to an ability to improve electrical reliability of transistors used.

    摘要翻译： 制造半导体器件避免晶体管泄漏电流的增加或耐压特性的降低是至少以下之一：衬垫氧化膜沿着衬底表面从沟槽的上边缘移除5至40的距离 nm：通过各向同性蚀刻在20nm内去除半导体衬底的暴露表面; 并且在氧（H2）与氧气（O2）的气体比小于或等于0.5的氧化环境中氧化形成在半导体衬底中的沟槽部分，实现曲率半径超过3nm的增加，而不会使风险 在槽分离结构中的上槽边缘部分处或附近在基板表面上产生任何水平差。 这消除了晶体管泄漏电流的增加或由于栅极电极膜的端部附近或周围的局部电场浓度而导致的耐压特性的降低，这进而导致提高使用的晶体管的电可靠性的能力 。

    Method for manufacturing semiconductor device
    6.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US6090684A

    公开(公告)日：2000-07-18

    申请号：US363184

    申请日：1999-07-29

    申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

    发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/78

    CPC分类号： H01L21/76232 ,  Y10S148/05

    摘要： A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.

    摘要翻译： 浅沟隔离结构（SGI）使半导体衬底上的相邻晶体管电绝缘。 在半导体基板上形成衬垫氧化膜，在衬垫氧化膜上形成氧化抑制膜。 除去氧化物抑制膜和垫氧化膜的一部分以形成槽。 特别地，在5〜40nm的范围内，从槽的上边缘去除衬垫氧化膜。 凹槽的区域在氢（H 2）与氧（O 2）的铸造比小于或等于0.5的氧化环境中被氧化。 在该比例下，在基板的上槽边缘处的低应力下氧化进行，从而能够在上槽边缘的四舍五入，而不会在基板表面上的上槽边缘处或附近产生水平差。

    Manufacturing method of semiconductor device
    8.
    发明申请
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US20080142901A1

    公开(公告)日：2008-06-19

    申请号：US12028593

    申请日：2008-02-08

    申请人： Shuji MATSUO ,  Katsuhiro Uchimura ,  Yasuko Yoshida ,  Kota Funayama ,  Yutaka Takeshima

    发明人： Shuji MATSUO ,  Katsuhiro Uchimura ,  Yasuko Yoshida ,  Kota Funayama ,  Yutaka Takeshima

    IPC分类号： H01L27/088

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

    摘要： A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

    摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成栅极绝缘膜和由多晶硅制成的栅电极; 将离子注入到半导体衬底中以形成作为源极或漏极的半导体区域; 在所述半导体衬底上形成钴膜和氮化钛膜以覆盖所述栅电极; 进行退火以引起Co和Si之间的反应以及半导体区域以形成CoSi层; 进行湿式清洗以除去氮化钛膜和未反应的钴膜，使CoSi层离开栅电极和半导体区域; 进行退火以引起CoSi层与栅极电极和半导体区域之间的反应以形成CoSi 2层; 进行HPM清洗; 以及通过低压CVD在半导体衬底上形成氮化硅膜以覆盖栅电极。

    Semiconductor memory device using vertical-channel transistors
    9.
    发明申请
    Semiconductor memory device using vertical-channel transistors 失效
    半导体存储器件采用垂直沟道晶体管

    公开(公告)号：US20050253143A1

    公开(公告)日：2005-11-17

    申请号：US11168872

    申请日：2005-06-29

    申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

    发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

    IPC分类号： G11C11/41 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/10

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

    摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

    摘要翻译： 本发明提供一种包括多个字线，多个位线以及多个静态存储单元的半导体存储器件，每个静态存储器单元具有第一，第二，第三，第四，第五和第六和第六晶体管。 尽管第一，第二，第三和第四晶体管的每个通道与半导体存储器件的衬底垂直地形成。 形成第五晶体管和第六晶体管的源极或漏极的半导体区域形成与衬底相反的PN结。 根据本发明的另一方面，本发明的SRAM器件具有多个SRAM单元，其中至少一个是在衬底上包括至少四个垂直晶体管的垂直SRAM单元，并且每个垂直晶体管包括源极， 排水管和其间的通道在以大于零度的角度穿入衬底表面的一个对准线对中。