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    Data processing device
    1.
    发明授权
    Data processing device 有权
    数据处理装置

    公开(公告)号：US07551493B2

    公开(公告)日：2009-06-23

    申请号：US11766341

    申请日：2007-06-21

    申请人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

    发明人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

    IPC分类号： G11C11/30

    CPC分类号： G11C16/0425

    摘要： A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

    摘要翻译： 一种数据处理装置，其选择来自非易失性存储单元的电子发射或向每一位注入电子。 存储器阵列包括多个非易失性存储单元，每个非易失性存储单元具有一对第一MOS晶体管和第二MOS晶体管，其中第一晶体管具有电荷保持层和存储栅极，并且用于数据存储，并且第二晶体管具有控制 并且选择性地将第一晶体管连接到位线。 当将负电压施加到存储器栅极时，由电荷保持层保持的电子通过在非易失性存储器单元通道区域中产生的热载流子发射以进行擦除; 并且当正电压施加到存储器栅极时，通过在非易失性存储器单元通道区域中产生的热载流子将电子注入电荷保持层中用于写入，并且通过每个位上的位线电压来控制热载流子的产生和抑制 线。

    Data processing device
    2.
    发明授权
    Data processing device 有权
    数据处理装置

    公开(公告)号：US07248504B2

    公开(公告)日：2007-07-24

    申请号：US11140741

    申请日：2005-06-01

    申请人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

    发明人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0425

    摘要： A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

    摘要翻译： 一种数据处理装置，其选择来自非易失性存储单元的电子发射或向每一位注入电子。 存储器阵列包括多个非易失性存储单元，每个非易失性存储单元具有一对第一MOS晶体管和第二MOS晶体管，其中第一晶体管具有电荷保持层和存储栅极，并且用于数据存储，并且第二晶体管具有控制 并且选择性地将第一晶体管连接到位线。 当将负电压施加到存储器栅极时，由电荷保持层保持的电子通过在非易失性存储器单元通道区域中产生的热载流子发射以进行擦除; 并且当正电压施加到存储器栅极时，通过在非易失性存储器单元通道区域中产生的热载流子将电子注入电荷保持层中用于写入，并且通过每个位上的位线电压来控制热载流子的产生和抑制 线。

    Semiconductor data processing device
    3.
    发明申请
    Semiconductor data processing device 有权
    半导体数据处理装置

    公开(公告)号：US20050128815A1

    公开(公告)日：2005-06-16

    申请号：US11002802

    申请日：2004-12-03

    申请人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

    发明人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

    IPC分类号： G11C16/02 ,  G11C7/00 ,  G11C16/06 ,  G11C16/16 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/16 ,  G11C16/30

    摘要： An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks each instructed to be erased together; and a control circuit, wherein the control circuit controls both of two kinds of erasing voltages applied to the nonvolatile memory cell in the erase block instructed to be erased together to select an erase sector from the erase block for performing erase for each erase sector, thereby performing the erase for each erase sector in time division. Time division erase can distribute an erasing current. Two kinds of erasing voltages are used to select the erase sector. No specific drivers need be provided for each erase sector.

    摘要翻译： 分配擦除电流以减少内部电源电路的负载并减少用于擦除的驱动器的数量。 一种半导体数据处理装置具有：存储阵列，其具有排列成矩阵状的非易失性存储单元，分为多个擦除块，分别被指示一起擦除; 以及控制电路，其中控制电路控制施加到擦除块中的非易失性存储单元的两种擦除电压，这些擦除块被一起擦除，以从擦除块中选择擦除扇区，以便为每个擦除扇区执行擦除，从而 按时间划分每个擦除扇区的擦除。 时分擦除可以分配擦除电流。 使用两种擦除电压来选择擦除扇区。 没有为每个擦除扇区提供特定的驱动程序。

    DATA PROCESSING DEVICE
    4.
    发明申请
    DATA PROCESSING DEVICE 有权
    数据处理设备

    公开(公告)号：US20070285984A1

    公开(公告)日：2007-12-13

    申请号：US11766341

    申请日：2007-06-21

    申请人： Akira KATO ,  Toshihiro Tanaka ,  Takashi Yamaki

    发明人： Akira KATO ,  Toshihiro Tanaka ,  Takashi Yamaki

    IPC分类号： G11C11/41

    CPC分类号： G11C16/0425

    摘要： A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

    摘要翻译： 一种数据处理装置，其选择来自非易失性存储单元的电子发射或向每一位注入电子。 存储器阵列包括多个非易失性存储单元，每个非易失性存储单元具有一对第一MOS晶体管和第二MOS晶体管，其中第一晶体管具有电荷保持层和存储栅极，并且用于数据存储，并且第二晶体管具有控制 并且选择性地将第一晶体管连接到位线。 当将负电压施加到存储器栅极时，由电荷保持层保持的电子通过在非易失性存储器单元通道区域中产生的热载流子发射以进行擦除; 并且当正电压施加到存储器栅极时，通过在非易失性存储器单元通道区域中产生的热载流子将电子注入电荷保持层中用于写入，并且通过每个位上的位线电压来控制热载流子的产生和抑制 线。

    Semiconductor data processing device
    5.
    发明授权
    Semiconductor data processing device 有权
    半导体数据处理装置

    公开(公告)号：US07110295B2

    公开(公告)日：2006-09-19

    申请号：US11002802

    申请日：2004-12-03

    申请人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

    发明人： Jiro Ishikawa ,  Takashi Yamaki ,  Toshihiro Tanaka ,  Yukiko Umemoto ,  Akira Kato

    IPC分类号： G11C16/04

    CPC分类号： G11C16/16 ,  G11C16/30

    摘要： An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks each instructed to be erased together; and a control circuit, wherein the control circuit controls both of two kinds of erasing voltages applied to the nonvolatile memory cell in the erase block instructed to be erased together to select an erase sector from the erase block for performing erase for each erase sector, thereby performing the erase for each erase sector in time division. Time division erase can distribute an erasing current. Two kinds of erasing voltages are used to select the erase sector. No specific drivers need be provided for each erase sector.

    摘要翻译： 分配擦除电流以减少内部电源电路的负载并减少用于擦除的驱动器的数量。 一种半导体数据处理装置具有：存储阵列，其具有排列成矩阵状的非易失性存储单元，分为多个擦除块，分别被指示一起擦除; 以及控制电路，其中控制电路控制施加到擦除块中的非易失性存储单元的两种擦除电压，这些擦除块被一起擦除，以从擦除块中选择擦除扇区，以便为每个擦除扇区执行擦除，从而 按时间划分每个擦除扇区的擦除。 时分擦除可以分配擦除电流。 使用两种擦除电压来选择擦除扇区。 没有为每个擦除扇区提供特定的驱动程序。

    Data processing device
    6.
    发明申请
    Data processing device 有权
    数据处理装置

    公开(公告)号：US20050270851A1

    公开(公告)日：2005-12-08

    申请号：US11140741

    申请日：2005-06-01

    申请人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

    发明人： Akira Kato ,  Toshihiro Tanaka ,  Takashi Yamaki

    IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/0425

    摘要： A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

    摘要翻译： 一种数据处理装置，其选择来自非易失性存储单元的电子发射或向每一位注入电子。 存储器阵列包括多个非易失性存储单元，每个非易失性存储单元具有一对第一MOS晶体管和第二MOS晶体管，其中第一晶体管具有电荷保持层和存储栅极，并且用于数据存储，并且第二晶体管具有控制 并且选择性地将第一晶体管连接到位线。 当将负电压施加到存储器栅极时，由电荷保持层保持的电子通过在非易失性存储器单元通道区域中产生的热载流子发射以进行擦除; 并且当正电压施加到存储器栅极时，通过在非易失性存储器单元通道区域中产生的热载流子将电子注入电荷保持层中用于写入，并且通过每个位上的位线电压来控制热载流子的产生和抑制 线。

    Nonvolatile memory device and semiconductor device
    7.
    发明申请
    Nonvolatile memory device and semiconductor device 有权
    非易失性存储器件和半导体器件

    公开(公告)号：US20060239072A1

    公开(公告)日：2006-10-26

    申请号：US11472993

    申请日：2006-06-23

    申请人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    发明人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/10 ,  G11C16/0433

    摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.

    摘要翻译： 这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

    Non-volatil semiconductor memory device and writing method thereof
    8.
    发明申请
    Non-volatil semiconductor memory device and writing method thereof 有权
    非挥发性半导体存储器件及其写入方法

    公开(公告)号：US20050285181A1

    公开(公告)日：2005-12-29

    申请号：US11147243

    申请日：2005-06-08

    申请人： Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

    发明人： Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

    IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/3418 ,  G11C16/0466 ,  G11C16/3427 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/792

    摘要： In a non-volatile semiconductor memory device using a charge storage film, it is intended to prevent a sequence disturb such as an erroneous write or erase of another memory cell on one and same word line which occurs depending on a bias transition path in stand-by state and write state. In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.

    摘要翻译： 在使用电荷存储膜的非易失性半导体存储器件中，旨在防止在根据独立的偏置过渡路径发生的同一字线上的另一个存储单元的错误写入或擦除的序列干扰， 按状态和写状态。 关于字线偏差的上升和下降，本发明采用使存储晶体管侧的扩散区电压Vs变化的过程，在电压Vs经过一定的中间值Vsx之后，栅极电压Vmg为 存储晶体管被改变。 或者，采用使存储晶体管的栅极电压Vmg改变的过程，并且在电压Vmg经过一定的中间值Vmgx之后，存储晶体管侧的扩散层电压Vs被改变。 Vsx和Vmgx的值由栅极绝缘膜中不引起FN隧穿电子注入的电场的大小确定，导致阈值电压的变化以及针对未引起BTBT热空穴注入的孔的势垒的大小。