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    APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY
    3.
    发明申请
    APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY 失效
    用于编程存储阵列的装置和方法

    公开(公告)号：US20060285393A1

    公开(公告)日：2006-12-21

    申请号：US11158518

    申请日：2005-06-21

    申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

    发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

    IPC分类号： G11C16/04

    CPC分类号： G11C17/18

    摘要： A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

    摘要翻译： 提供了一种对存储器阵列进行编程的方法，包括通过相对于各个字线相互依次提供多个电压步骤来访问存储器阵列的多个字线，以及每个存储器阵列的多个位线 访问相应字线的时间，对与同时访问的各个字和位线相对应的多个设备进行编程，每个设备通过断开设备的介电层进行编程，访问位线被排序，使得只有 一个设备中的单个设备一次被编程。

    Memory cell driver circuits
    4.
    发明申请
    Memory cell driver circuits 有权
    存储单元驱动电路

    公开(公告)号：US20060291265A1

    公开(公告)日：2006-12-28

    申请号：US11169106

    申请日：2005-06-27

    申请人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

    发明人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

    IPC分类号： G11C17/00

    CPC分类号： G11C17/18

    摘要： A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

    摘要翻译： 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍， 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。

    Decoupling capacitors for thin gate oxides
    6.
    发明授权
    Decoupling capacitors for thin gate oxides 有权
    薄栅氧化物去耦电容器

    公开(公告)号：US06828638B2

    公开(公告)日：2004-12-07

    申请号：US09469406

    申请日：1999-12-22

    申请人： Ali Keshavarzi ,  Vivek K. De ,  Tanay Karnik ,  Rajendran Nair

    发明人： Ali Keshavarzi ,  Vivek K. De ,  Tanay Karnik ,  Rajendran Nair

    IPC分类号： H01L2976

    CPC分类号： H01L27/0805 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.

    摘要翻译： 在一些实施例中，本发明涉及具有承载电源电压的第一导体和承载接地电压的第二导体的管芯。 以耗尽模式工作的半导体电容器耦合在第一和第二导体之间，以在第一和第二导体之间提供去耦电容，半导体电容器具有栅极电压。 可以使用各种构造，包括：n体中的n +栅极多晶硅和n +源极/漏极区域; p +栅极多晶硅和n +源极/漏极区域; p +栅极poly和p +源极/漏极区域在n体中; p体中的p +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和n +源极/漏极区域。 电源电压可能比平带电压具有更大的绝对值。

    Memory cell driver circuits
    7.
    发明授权
    Memory cell driver circuits 有权
    存储单元驱动电路

    公开(公告)号：US07236410B2

    公开(公告)日：2007-06-26

    申请号：US11169106

    申请日：2005-06-27

    申请人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Vivek K. De

    发明人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Vivek K. De

    IPC分类号： G11C7/00 ,  G11C17/00 ,  G11C5/06

    CPC分类号： G11C17/18

    摘要： A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

    摘要翻译： 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍， 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。