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153 条记录 (耗时 0.025 秒)

    Method for monitoring focus on an integrated wafer
    1.
    发明授权
    Method for monitoring focus on an integrated wafer 有权
    用于监控集成晶圆的方法

    公开(公告)号：US09046788B2

    公开(公告)日：2015-06-02

    申请号：US12122929

    申请日：2008-05-19

    申请人： Allen H. Gabor ,  Wai-Kin Li

    发明人： Allen H. Gabor ,  Wai-Kin Li

    IPC分类号： G03B27/52 ,  G03B27/68 ,  G03F7/20

    CPC分类号： G03F7/70333 ,  G03F7/70508 ,  G03F7/70641

    摘要： A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value.

    摘要翻译： 提供了一种用于在半导体制造工艺的光刻成像过程期间改善诸如晶片之类的衬底的聚焦的方法和装置。 本发明对于步进扫描系统特别有用，并且每个曝光场中的两个特征的CD在以不同焦点曝光的场中测量以形成至少两个Bossung曲线。 基于曲线的交点，然后基于计算出的曝光聚焦指令对晶片进行扫描和成像，计算曝光对焦指令。 在本发明的另一方面，当正在处理多个晶片时，操作方差可能导致焦点漂移。 可以通过测量每个特征的临界尺寸并比较差异来确定是否需要任何聚焦偏移以将焦点返回到原始计算的聚焦值，从而容易地校正聚焦漂移。

    METHOD FOR MONITORING FOCUS ON AN INTEGRATED WAFER
    2.
    发明申请
    METHOD FOR MONITORING FOCUS ON AN INTEGRATED WAFER 有权
    用于监测聚合波的聚焦方法

    公开(公告)号：US20090284722A1

    公开(公告)日：2009-11-19

    申请号：US12122929

    申请日：2008-05-19

    申请人： Allen H. Gabor ,  Wai-Kin Li

    发明人： Allen H. Gabor ,  Wai-Kin Li

    IPC分类号： G03B27/42 ,  G06K9/00

    CPC分类号： G03F7/70333 ,  G03F7/70508 ,  G03F7/70641

    摘要： A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value.

    摘要翻译： 提供了一种用于在半导体制造工艺的光刻成像过程期间改善诸如晶片之类的衬底的聚焦的方法和装置。 本发明对于步进扫描系统特别有用，并且每个曝光场中的两个特征的CD在以不同焦点曝光的场中测量以形成至少两个Bossung曲线。 基于曲线的交点，然后基于计算出的曝光聚焦指令对晶片进行扫描和成像，计算曝光对焦指令。 在本发明的另一方面，当正在处理多个晶片时，操作方差可能导致焦点漂移。 可以通过测量每个特征的临界尺寸并比较差异来确定是否需要任何聚焦偏移以将焦点返回到原始计算的聚焦值，从而容易地校正聚焦漂移。

    Directed self-assembly of block copolymers using segmented prepatterns
    4.
    发明授权
    Directed self-assembly of block copolymers using segmented prepatterns 有权
    使用分段预制图的嵌段共聚物的定向自组装

    公开(公告)号：US08398868B2

    公开(公告)日：2013-03-19

    申请号：US12468391

    申请日：2009-05-19

    申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders

    发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders

    IPC分类号： B44C1/22 ,  H01L21/302 ,  H01L21/312

    CPC分类号： B81C1/00031 ,  B81C1/00404 ,  B81C2201/0149 ,  H01L21/0337 ,  H01L21/31144

    摘要： An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls.

    摘要翻译： 例如使用光刻法形成衬底中的开口，其中开口具有侧壁，其横截面由轮廓和凸形的部分给出。 例如，开口的横截面可以由重叠的圆形区域给出。 侧壁在各个点处相邻，在那里它们限定突起。 将包含嵌段共聚物的聚合物层施加在开口和基底上，并允许自组装。 在开口中形成离散的，分离的畴，其被去除以形成孔，其可以转移到下面的基底中。 这些区域及其对应的孔的位置通过侧壁及其相关联的突起被引导到预定位置。 分离这些孔的距离可以大于或小于如果嵌段共聚物（和任何添加剂）在没有任何侧壁的情况下自组装就会发生。

    Integration process to improve focus leveling within a lot process variation
    5.
    发明授权
    Integration process to improve focus leveling within a lot process variation 有权
    整合过程可以在很多过程变化中提高焦点调平

    公开(公告)号：US08395228B2

    公开(公告)日：2013-03-12

    申请号：US12941375

    申请日：2010-11-08

    申请人： Wai-Kin Li ,  Wu-Song Huang ,  Dario Leonardo Goldfarb ,  Martin Glodde ,  Edward Engbrecht ,  Yiheng Xu

    发明人： Wai-Kin Li ,  Wu-Song Huang ,  Dario Leonardo Goldfarb ,  Martin Glodde ,  Edward Engbrecht ,  Yiheng Xu

    IPC分类号： H01L21/02

    CPC分类号： H01L21/0332 ,  G03F7/091 ,  G03F7/094 ,  G03F9/7026

    摘要： A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.

    摘要翻译： 描述了改善半导体晶片的聚焦调平响应的方法。 该方法包括在半导体衬底上组合有机和无机或金属近红外（NIR）硬掩模; 在组合的有机NIR吸收和无机或金属NIR吸收硬掩模上形成抗反射涂层（ARC）层; 以及在所述ARC层上形成光致抗蚀剂层。 还描述了半导体结构，其包括基板，位于结构上方的抗蚀剂层; 以及位于衬底上方的吸收层。 吸收层包括无机或金属NIR吸收硬掩模层。

    Method for removing threshold voltage adjusting layer with external acid diffusion process
    6.
    发明授权
    Method for removing threshold voltage adjusting layer with external acid diffusion process 有权
    用外部酸性扩散法去除阈值电压调节层的方法

    公开(公告)号：US08227307B2

    公开(公告)日：2012-07-24

    申请号：US12490353

    申请日：2009-06-24

    申请人： Kuang-Jung Chen ,  Ricardo A. Donaton ,  Wu-Song Huang ,  Wai-Kin Li

    发明人： Kuang-Jung Chen ,  Ricardo A. Donaton ,  Wu-Song Huang ,  Wai-Kin Li

    IPC分类号： H01L21/8238 ,  H01L21/31

    CPC分类号： H01L21/31122 ,  H01L21/823842 ,  H01L21/823857

    摘要： The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid.

    摘要翻译： 本发明提供一种形成阈值电压调节的栅极叠层的方法，其中使用外部酸扩散工艺来从半导体衬底的一个器件区域选择性地去除一部分阈值电压调节层。 外部酸扩散方法使用酸性聚合物，其在烘烤时表现出酸浓度的增加，其可以扩散到阈值电压调节层的下部暴露部分。 扩散的酸与阈值电压调节层的暴露部分反应，提供酸反应层，与不暴露于扩散的酸的阈值电压调节层的横向相邻部分相比，可以选择性地除去酸反应层。

    PHOTORESIST COMPOSITIONS AND METHODS FOR SHRINKING A PHOTORESIST CRITICAL DIMENSION
    8.
    发明申请
    PHOTORESIST COMPOSITIONS AND METHODS FOR SHRINKING A PHOTORESIST CRITICAL DIMENSION 失效
    光电复合材料组合物和方法，用于收缩光刻胶关键尺寸

    公开(公告)号：US20120070787A1

    公开(公告)日：2012-03-22

    申请号：US12883442

    申请日：2010-09-16

    申请人： Wu-Song Huang ,  Kuang-Jung Chen ,  Wai-Kin Li ,  Sen Liu

    发明人： Wu-Song Huang ,  Kuang-Jung Chen ,  Wai-Kin Li ,  Sen Liu

    IPC分类号： G03F7/20

    CPC分类号： G03F7/40 ,  G03F7/0045 ,  G03F7/0397 ,  G03F7/405

    摘要： A method for reducing a photoresist critical dimension, the method comprising depositing a photoresist film on a substrate, wherein the photoresist film includes a thermal base generator; patterning the photoresist film to form a first patterned film possessing a first critical dimension; depositing a crosslinkable film over the first patterned film; heat-activating the first patterned film, either before or after depositing the crosslinkable film, to release a base in the first patterned film and cause crosslinking in the crosslinkable film in contact with the first patterned film; and developing the crosslinkable film to remove non-crosslinked soluble portions therein to form a second patterned film possessing a reduced critical dimension compared to the first critical dimension.

    摘要翻译： 一种降低光致抗蚀剂临界尺寸的方法，所述方法包括在基底上沉积光致抗蚀剂膜，其中光致抗蚀剂膜包括热碱发生器; 图案化光致抗蚀剂膜以形成具有第一临界尺寸的第一图案化膜; 在第一图案化膜上沉积可交联膜; 在沉积可交联膜之前或之后热激活第一图案化膜，以释放第一图案化膜中的碱，并引起与第一图案化膜接触的可交联膜的交联; 并且显影所述可交联膜以除去其中的非交联的可溶部分以形成与第一临界尺寸相比具有降低的临界尺寸的第二图案化膜。

    Gate Conductor Structure
    10.
    发明申请
    Gate Conductor Structure 有权
    门导体结构

    公开(公告)号：US20110156282A1

    公开(公告)日：2011-06-30

    申请号：US13010009

    申请日：2011-01-20

    申请人： Wai-Kin Li ,  Haining Yang

    发明人： Wai-Kin Li ,  Haining Yang

    IPC分类号： H01L29/423

    CPC分类号： H01L21/76841 ,  H01L21/823842 ,  H01L21/823871 ,  H01L22/12 ,  H01L23/58 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.

    摘要翻译： 提供了具有在N型器件和P型器件之间的势垒区域的栅极导体结构，其中所述势垒区域最小化或消除了所述阻挡区域上的掺杂剂物质的交叉扩散。 阻挡区域包括栅极导体结构中的至少一个亚光刻间隙。 通过使用自组装共聚物在栅极导体结构上形成亚光刻图案掩模来形成亚光刻间隙。 根据一个实施例，至少一个亚光刻间隙是穿过栅极导体结构的宽度的狭缝或线。 亚光刻间隙足够深以使注入的掺杂剂从栅极导体的上部最小化或防止交叉扩散。 根据另一个实施例，亚光刻间隙具有足够的密度，使得在激活退火期间掺杂剂的交叉扩散减少或消除，使得Vt的变化最小化。