公开(公告)号：US5237535A

公开(公告)日：1993-08-17

申请号：US773228

申请日：1991-10-09

申请人： Neal Mielke ,  Gregory E. Atwood ,  Amit Merchant

发明人： Neal Mielke ,  Gregory E. Atwood ,  Amit Merchant

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/14 ,  G11C16/34 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G11C29/52

CPC分类号： G11C29/82 ,  G11C16/14 ,  G11C16/3404 ,  G11C16/3409 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C29/52 ,  G11C29/88 ,  G06F2201/81 ,  G11B2220/2545 ,  G11C16/04 ,  G11C2029/5006

摘要： A method of repairing overerased cells in a flash memory array including a column having a first cell and a second cell is described. Repair begins by determining whether a first cell is overerased and applying a programming pulse if so. Next, the second cell is examined to determine whether it is overerased. A programming pulse is applied to the second cell if it is overerased. Afterward, if either of the cells was overerased then the repair pulse voltage level is incremented. These steps are repeated until none of the cells on the column is identified as overerased.

摘要翻译： 描述了在包括具有第一单元和第二单元的列的闪存阵列中修复过度曝光单元的方法。 修复开始于确定第一个单元是否过高，如果是，则应用编程脉冲。 接下来，检查第二个单元以确定是否过高。 如果编程脉冲过高，则将其应用于第二个单元。 之后，如果任一个单元被过渡，则修复脉冲电压电平增加。 重复这些步骤，直到列上的单元格都被识别为过高。

公开(公告)号：US5327383A

公开(公告)日：1994-07-05

申请号：US871485

申请日：1992-04-21

申请人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

发明人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C29/82 ,  G11C16/10 ,  G11C16/16

摘要： Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure. The circuitry also includes a postcondition controller and a program controller.

摘要翻译： 描述用于独立地控制闪存的擦除的电路，包括用于替换存储器阵列内的短路行的冗余行。 擦除命令将触发一个定序器电路，该电路对执行擦除事件任务的控制器进行调度。 通过嵌套擦除事件的控制，定序器电路允许轻松修改擦除事件。 定序器电路在接收到擦除命令时触发前提条件控制器。 前置条件控制器然后管理存储器阵列的预处理，包括短路行内的存储器单元。 前提条件控制器通过禁用用冗余行替换短路行来做到这一点。 在预处理期间，在存储单元被擦除为逻辑1之前，每个存储器单元被编程为逻辑0，以防止在后续擦除期间存储器单元的过度擦写。 之后，序列发生器触发擦除控制器。 然后擦除控制电路管理擦除。 电路还包括后置条件控制器和程序控制器。

公开(公告)号：US5377147A

公开(公告)日：1994-12-27

申请号：US105871

申请日：1993-08-11

申请人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

发明人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC分类号： G11C29/82 ,  G11C16/3445 ,  G11C16/3468 ,  G11C16/3477

摘要： Circuitry for verifying the preconditioning of shorted cells within a flash memory cell. The preconditioning circuitry accommodates shorted cells, allowing them to pass verification at lower threshold voltage levels than good cells but ensuring the threshold voltage levels of shorted cells are high enough to prevent bitline leakage. The circuitry includes a sense amplifier for comparing the threshold voltage of a memory cell within the memory array to a selected reference threshold voltage level. The sense amplifier indicates whether the array memory cells exceeds the selected reference threshold voltage level. Selection circuitry couples two different reference cells to the sense amplifier, each having a different threshold voltage level. One of the reference cells has a normal threshold voltage level; i.e., a threshold voltage level to which good cells should be preconditioned. The other reference cell, a shorted reference cell, has a threshold voltage less than the nominal threshold voltage, but sufficient to prevent the quick overerasure of array cells during erasure. When the array cell is shorted to another cell within the array, selection circuitry selects the shorted reference cell. Otherwise, the other reference cell is selected.

摘要翻译： 用于验证闪存单元内的短路单元的预处理的电路。 预处理电路容纳短路单元，允许它们在比较好的单元更低的阈值电压电平下通过验证，但是确保短路单元的阈值电压电平足够高以防止位线泄漏。 该电路包括读出放大器，用于将存储器阵列内的存储单元的阈值电压与选定的参考阈值电压电平进行比较。 读出放大器指示阵列存储单元是否超过选定的参考阈值电压电平。 选择电路将两个不同的参考单元耦合到读出放大器，每个具有不同的阈值电压电平。 一个参考单元具有正常的阈值电压电平; 即要预处理好电池的阈值电压电平。 另一个参考单元，短路参考单元，具有小于标称阈值电压的阈值电压，但足以防止在擦除期间阵列单元的快速过渡。 当阵列单元与阵列内的另一单元短路时，选择电路选择短路参考单元。 否则，选择另一个参考单元。

公开(公告)号：US5347489A

公开(公告)日：1994-09-13

申请号：US871848

申请日：1992-04-21

申请人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

发明人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC分类号： G11C29/82 ,  G11C16/3445 ,  G11C16/3468 ,  G11C16/3477

摘要： A method of preconditioning and verifying the preconditioning of memory cells within shorted rows of a memory array is described. Preconditioning begins by applying a preconditioning pulse to two memory cells that are shorted together. Afterward, one of the two shorted cells is read by applying a nominal gate voltage level to the gates of both of the shorted memory cells. At the same time, a shorted reference cell is read by applying a voltage level to its gate which less than the nominal gate voltage level. While the read voltages are being applied to the array cells and the shorted reference cell, the threshold voltage of one of the two shorted array cells is compared to the threshold voltage of the shorted reference cell. The shorted reference cell has a threshold voltage level that is lower than the level normally required for preconditioning but which is sufficient to prevent the quick overerasure of the shorted memory cells.

摘要翻译： 描述了一种对存储器阵列的短行内的存储单元进行预处理和验证预处理的方法。 预处理开始于将预处理脉冲应用于短路在一起的两个存储单元。 之后，通过对两个短路存储器单元的栅极施加标称栅极电压电平来读取两个短路单元之一。 同时，通过向其栅极施加小于额定栅极电压电平的电压电平来读取短路参考电池。 当读取电压被施加到阵列单元和短路参考单元时，将两个短路阵列单元之一的阈值电压与短路参考单元的阈值电压进行比较。 短路参考电池具有低于预处理通常所需的电平的阈值电压电平，但足以防止短路存储器单元的快速过热。

公开(公告)号：US08898434B2

公开(公告)日：2014-11-25

申请号：US13294244

申请日：2011-11-11

申请人： Amit Merchant ,  Dipankar Sarma ,  Vaidyanathan Srinivasan

发明人： Amit Merchant ,  Dipankar Sarma ,  Vaidyanathan Srinivasan

IPC分类号： G06F9/52 ,  G06F11/34 ,  G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/52 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/865

摘要： A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.

公开(公告)号：US06772322B1

公开(公告)日：2004-08-03

申请号：US09489141

申请日：2000-01-21

申请人： Amit Merchant ,  Selim Bilgin ,  Brinkley Sprunt

发明人： Amit Merchant ,  Selim Bilgin ,  Brinkley Sprunt

IPC分类号： G06F1500

CPC分类号： G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88

摘要： A method and apparatus to monitor the performance of a processor. A performance specifier specifies a performance data corresponding to the performance. The performance data includes an event and an instruction causing the event. A tag generator is coupled to the performance specifier to generate a performance tag associated with the instruction. The performance tag is stored in a storage. A retirement performance monitor is coupled to the storage to extract the performance tag when the instruction is retired.

摘要翻译： 一种监视处理器性能的方法和装置。 性能说明符指定与性能相对应的性能数据。 性能数据包括引起事件的事件和指令。 标签发生器耦合到性能说明符以产生与指令相关联的性能标签。 性能标签存储在存储器中。 退出性能监视器耦合到存储器以在指令退出时提取性能标签。

公开(公告)号：US5682516A

公开(公告)日：1997-10-28

申请号：US205023

申请日：1994-03-01

申请人： Nitin V. Sarangdhar ,  Wen Han Wang ,  Michael W. Rhodehamel ,  James M. Brayton ,  Amit Merchant ,  Matthew A. Fisch

发明人： Nitin V. Sarangdhar ,  Wen Han Wang ,  Michael W. Rhodehamel ,  James M. Brayton ,  Amit Merchant ,  Matthew A. Fisch

IPC分类号： G06F12/08 ,  G06F13/368 ,  H04L29/06 ,  G06F13/18

CPC分类号： G06F12/0831 ,  G06F13/368 ,  H04L29/06 ,  G06F12/0813

摘要： A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.

摘要翻译： 公开了一种计算机系统，其具有通过总线发布通信事务的请求总线代理和用于延迟通信事务以避免高总线等待时间的寻址总线代理。 所处理的总线代理商随后通过总线发出延迟回复交易，以完成通信交易。 特殊侦听所有权和缓存状态转换规则在延迟通信事务期间保持缓存一致性和处理器一致性。

公开(公告)号：US07353370B2

公开(公告)日：2008-04-01

申请号：US11040773

申请日：2005-01-20

申请人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu ,  Keshavan Tiruvallur

发明人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu ,  Keshavan Tiruvallur

IPC分类号： G06F9/38

CPC分类号： G06F9/3851

摘要： A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.

摘要翻译： 系统包括多线程处理器，用于存储多个线程的存储器以及将多个线程传送到多线程处理器的总线。 多线程处理器包括事件检测器，用于检测第一线程的第一事件指示。 响应于对第一线程的第一事件指示的检测，事件检测器监视在多线程处理器内正在处理的第二线程以检测第二线程的清零点，并且响应于检测到第二线程的清除点 线程至少清除第一个线程的多线程处理器内的功能单元。

公开(公告)号：US20130124826A1

公开(公告)日：2013-05-16

申请号：US13294244

申请日：2011-11-11

申请人： Amit Merchant ,  Dipankar Sarma ,  Vaidyanathan Srinivasan

发明人： Amit Merchant ,  Dipankar Sarma ,  Vaidyanathan Srinivasan

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/52 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/865

摘要： A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.

摘要翻译： 一种用于优化中央处理单元核心（CPU）中的程序指令执行吞吐量的技术。 CPU实现同时多线程（SMT）操作模式，其中与至少两个软件线程相关联的程序指令作为硬件线程并行执行，同时共享CPU使用的一个或多个硬件资源，例如高速缓冲存储器，翻译后备缓冲器，功能 执行单元等。作为SMT模式的一部分，CPU实现自动线程（AT）操作模式。 在AT操作模式期间，确定是否存在破坏指令执行吞吐量的硬件线程之间的资源冲突。 如果检测到资源冲突，则CPU根据软件线程的相对优先级来调整硬件线程的相对指令执行速率。

公开(公告)号：US20050132376A1

公开(公告)日：2005-06-16

申请号：US11040773

申请日：2005-01-20

申请人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu ,  Keshavan Tiruvallur

发明人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu ,  Keshavan Tiruvallur

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3851

摘要： A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.

摘要翻译： 系统包括多线程处理器，用于存储多个线程的存储器以及将多个线程传送到多线程处理器的总线。 多线程处理器包括事件检测器，用于检测第一线程的第一事件指示。 响应于对第一线程的第一事件指示的检测，事件检测器监视在多线程处理器内正在处理的第二线程以检测第二线程的清零点，并且响应于检测到第二线程的清除点 线程至少清除第一个线程的多线程处理器内的功能单元。