公开(公告)号：US5267118A

公开(公告)日：1993-11-30

申请号：US843701

申请日：1992-02-28

申请人： Andrew Marshall ,  Kenneth G. Buss ,  David R. Cotton

发明人： Andrew Marshall ,  Kenneth G. Buss ,  David R. Cotton

IPC分类号： H02H5/04

CPC分类号： H02H5/044

摘要： Circuitry (46, or 28 and 70) for thermally separating a power integrated circuit device (12) from a plurality of other such devices (14, 16, and 18) on a common power integrated circuit chip (10) operate when the device (12) reaches a thermal shutdown temperature setpoint (56) with an output current at a predetermined current limit (54). The circuitry 46, or 28 and 70 switches the output current to a shutdown current level (57) until the device (12) reaches a predetermined lower temperature setpoint (58). Circuitry (46, or 28 and 70) restores the output current level to the predetermined current limit only after the device (12) reaches both the predetermined lower temperature setpoint (58) and a predetermined circuit setpoint (62 or 74). The circuit setpoint (62 or 74) associates with the temperature of the device (12) and may be either a yet lower temperature setpoint (62) or a specified time delay (74). The above steps are repeated to lower the average temperature of the device (12) and thereby thermally separate the device (12) from the other of such devices (14, 16 and 18) on the common power integrated circuit chip (10).

摘要翻译： 用于将功率集成电路器件（12）与公共功率集成电路芯片（10）上的多个其它这样的器件（14,16和18）热分离的电路（46或28和70）在器件 12）以预定电流极限（54）的输出电流达到热关断温度设定点（56）。 电路46或28和70将输出电流切换到关断电流电平（57），直到装置（12）达到预定的较低温度设定点（58）。 只有在设备（12）达到预定的较低温度设定点（58）和预定的电路设定点（62或74）之后，电路（46或28和70）才将输出电流电平恢复到预定电流限制。 电路设定点（62或74）与设备（12）的温度相关联，并且可以是较低温度设定点（62）或指定的时间延迟（74）。 重复上述步骤以降低装置（12）的平均温度，从而将装置（12）与公共功率集成电路芯片（10）上的另一个装置（14,16和18）热分离。

公开(公告)号：US5691940A

公开(公告)日：1997-11-25

申请号：US656553

申请日：1996-05-31

申请人： Andrew Marshall ,  Kenneth G. Buss ,  Ross E. Teggatz ,  Joe A. Devore

发明人： Andrew Marshall ,  Kenneth G. Buss ,  Ross E. Teggatz ,  Joe A. Devore

IPC分类号： G01R31/30 ,  G06F1/30 ,  G11C11/34

CPC分类号： G01R31/3004 ,  G06F1/30

摘要： A method and apparatus for programmable current limits is provided in which a plurality of current limit programmable cells (44 and 46) are programmed with a current limit. Output circuitry (14 and 16) which outputs current is limited by current limit circuitry (20, 24, 38, 40, and 42) when the output current reaches the programmed current limit.

摘要翻译： 提供了一种用于可编程电流限制的方法和装置，其中多个限流可编程单元（44和46）被编程为电流限制。 当输出电流达到编程电流极限时，输出电流的输出电路（14和16）受限流电路（20,24,38,40和42）限制。

公开(公告)号：US20150146834A1

公开(公告)日：2015-05-28

申请号：US14235242

申请日：2011-07-25

申请人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

发明人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

IPC分类号： H04L7/033

CPC分类号： H04L7/0331 ,  H03L7/0807 ,  H04L7/0025 ,  H04L7/0045 ,  H04L7/005 ,  H04L7/033 ,  H04L25/20

摘要： A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

摘要翻译： 提供了一种用于减少数字信号中的抖动的电路，包括时钟和数据恢复级，用于接收输入数据信号，并响应于此产生恢复的数据信号，恢复的时钟信号和未滤波的内插器代码; 滤波器级，用于接收未滤波的内插器代码并响应于其产生经滤波的时钟信号; 以及存储组件，用于接收恢复的数据信号，恢复的时钟信号和经滤波的时钟信号; 使用恢复的时钟信号对恢复的数据信号进行采样; 存储所得到的采样位; 并通过使用滤波的时钟信号选择存储的比特来产生输出数据信号。

公开(公告)号：US08927022B2

公开(公告)日：2015-01-06

申请号：US13511971

申请日：2010-03-03

申请人： Max Maginness ,  Andrew Marshall ,  Christine L. Glaister ,  Michel Alvarez

发明人： Max Maginness ,  Andrew Marshall ,  Christine L. Glaister ,  Michel Alvarez

IPC分类号： A61K9/14 ,  C08B37/00 ,  B02C23/08 ,  C08F20/28 ,  C08J9/26 ,  A61K38/18 ,  C08G77/04 ,  A61L27/52 ,  A61L27/56 ,  A61L27/54 ,  A61L27/58

CPC分类号： A61L27/58 ,  A61L27/52 ,  A61L27/54 ,  A61L27/56 ,  A61L2300/406 ,  A61L2300/414 ,  A61L2400/06 ,  A61L2400/10

摘要： The disclosure provides granular forms of porous biomaterials and methods for forming and applying these biomaterials, including uses to promote vascularization and tissue ingrowth.

摘要翻译： 本公开提供了多孔生物材料的颗粒形式和形成和应用这些生物材料的方法，包括促进血管形成和组织向内生长的用途。

公开(公告)号：US08500390B2

公开(公告)日：2013-08-06

申请号：US12783937

申请日：2010-05-20

申请人： Czeslaw Wojtyczka ,  Andrew Marshall

发明人： Czeslaw Wojtyczka ,  Andrew Marshall

IPC分类号： F01B25/16 ,  F01D21/00

CPC分类号： F01D21/045 ,  F01D11/122 ,  F01D11/127 ,  F04D29/526 ,  F05D2260/96

摘要： A turbofan engine comprising an annular inner wall surrounding tips of the fan blades, a layer of insulating material surrounding the inner wall, and an outer casing including an annular outer wall surrounding the insulating material and concentric to the inner wall and at least two annular rub elements extending radially inwardly from the outer wall through only part of a radial thickness of the layer of insulating material, at least two of the rub elements being in axial alignment with the blade tips at every point around a circumference of the fan, each rub element having a radially inner end spaced apart from the inner wall and made of a material harder than that of the blades, and a containment fabric layer wrapped around a support structure of the outer wall.

摘要翻译： 一种涡轮风扇发动机，其包括围绕所述风扇叶片的尖端的环形内壁，围绕所述内壁的绝缘材料层，以及外壳，所述外壳包括围绕所述绝缘材料并与所述内壁同心的环形外壁和至少两个环形摩擦 元件从外壁径向向内延伸穿过绝缘材料层的径向厚度的一部分，至少两个摩擦元件在风扇圆周周围的每个点处与叶片尖端轴向对准，每个摩擦元件 具有与所述内壁间隔开并由比所述叶片更硬的材料制成的径向内端，以及围绕所述外壁的支撑结构缠绕的容纳织物层。

公开(公告)号：US08318193B2

公开(公告)日：2012-11-27

申请号：US13156966

申请日：2011-06-09

申请人： Buddy D. Ratner ,  Andrew Marshall

发明人： Buddy D. Ratner ,  Andrew Marshall

IPC分类号： A61F2/02

CPC分类号： A61F2/0077 ,  A61F2/06 ,  A61L27/14 ,  A61L27/56

摘要： The invention provides crosslinked porous biomaterials and methods for forming crosslinked porous biomaterials. The crosslinked porous biomaterials of the invention comprise a biocompatible polymer scaffold defining an array of pores, wherein substantially all the pores have a similar diameter, wherein the mean diameter of the pores is between about 20 and about 90 micrometers, wherein substantially all the pores are each connected to at least 4 other pores, and wherein the diameter of substantially all the connections between the pores is between about 15% and about 40% of the mean diameter of the pores. The invention also provides implantable devices comprising a layer of a biomaterial, and methods for promoting angiogenesis in and around an implantable biomaterial.

摘要翻译： 本发明提供交联的多孔生物材料和形成交联的多孔生物材料的方法。 本发明的交联的多孔生物材料包括限定孔阵列的生物相容性聚合物支架，其中基本上所有的孔具有相似的直径，其中孔的平均直径为约20至约90微米，其中基本上所有的孔为 每个连接到至少4个其它孔，并且其中孔之间的基本上所有连接的直径在孔的平均直径的约15％至约40％之间。 本发明还提供了包括生物材料层的可植入装置，以及用于在可植入生物材料内和周围促进血管生成的方法。

公开(公告)号：US20120019263A1

公开(公告)日：2012-01-26

申请号：US12839532

申请日：2010-07-20

申请人： Andrew Marshall ,  Md. Imran Hossain ,  Michelle N. Nguyen

发明人： Andrew Marshall ,  Md. Imran Hossain ,  Michelle N. Nguyen

IPC分类号： G01R27/26

CPC分类号： G01R27/2605 ,  G01R31/2637

摘要： Circuitry and methods for measuring capacitive mismatch with improved precision. The capacitors under measurement are connected in series in a voltage divider, with the node common to both capacitors connected to the gate of a source follower transistor. In one disclosed embodiment of the invention, a ramped voltage is applied to the drain of the source follower transistor simultaneously with the ramped voltage applied to the voltage divider; the slope of the ramped drain voltage is at the nominal slope of the voltage at the common node of the voltage divider. In another embodiment, a second transistor in saturation has its gate coupled to the source of the source follower device, and its source connected to the drain of the source follower device in series with a constant voltage drop. The drain-to-source voltage of the source follower device is thus held constant in each embodiment, improving precision of the measurement.

摘要翻译： 用于测量电容失配的电路和方法，提高精度。 测量的电容器串联连接在分压器中，两个电容器的公共端连接到源极跟随器晶体管的栅极。 在本发明的一个公开的实施例中，斜坡电压与施加到分压器的斜坡电压同时施加到源极跟随器晶体管的漏极; 斜坡漏极电压的斜率为分压器公共节点处电压的额定斜率。 在另一个实施例中，饱和的第二晶体管的栅极耦合到源极跟随器件的源极，并且其源极与恒定的电压降串联连接到源极跟随器件的漏极。 因此，在每个实施例中，源极跟随器件的漏极 - 源极电压保持恒定，从而提高了测量的精度。

公开(公告)号：US07952378B2

公开(公告)日：2011-05-31

申请号：US12358510

申请日：2009-01-23

申请人： Andrew Marshall ,  Vijay Kumar Reddy

发明人： Andrew Marshall ,  Vijay Kumar Reddy

IPC分类号： G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/2856

摘要： Apparatus and methods are disclosed for examining how reliability in an RF power amplifier circuit changes as a function of variation of the input to output voltage swings. Two output transistors that varying greatly in the size of their respective channel widths are provided for independently evaluating impacts on the output waveform. The gate control for the smaller transistor is separate from the gate control to the larger transistor. The gate and drain stress can thus be adjusted and evaluated independently.

摘要翻译： 公开了用于检查RF功率放大器电路中的可靠性如何随着输入到输出电压摆幅的变化而变化的装置和方法。 提供两个输出晶体管，它们各自的通道宽度的大小变化很大，用于独立评估对输出波形的影响。 较小晶体管的栅极控制与栅极控制分离到较大的晶体管。 因此可以独立地调节和评估栅极和漏极应力。

公开(公告)号：US07907456B2

公开(公告)日：2011-03-15

申请号：US11931098

申请日：2007-10-31

申请人： Theodore W. Houston ,  Andrew Marshall

发明人： Theodore W. Houston ,  Andrew Marshall

IPC分类号： G11C5/14 ,  G11C11/00

CPC分类号： G11C5/14 ,  G11C8/08 ,  G11C11/413

摘要： An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. A voltage differential generating circuit is operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein the differential is a function of the array supply voltage.

摘要翻译： 集成电路（IC）包括至少一个存储器阵列，其具有以多个行和列排列的多个存储器单元，该阵列还具有用于访问单元行的多个字线和用于访问列的列的多个位线 细胞。 电压差分发生电路可操作以提供相对于阵列电源电压的差分字线电压（VWL），其中差分是阵列电源电压的函数。

公开(公告)号：US07842955B2

公开(公告)日：2010-11-30

申请号：US12700479

申请日：2010-02-04

申请人： Ashesh Parikh ,  Andrew Marshall

发明人： Ashesh Parikh ,  Andrew Marshall

IPC分类号： H01L29/15 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L51/055 ,  B82Y10/00 ,  H01L51/0002 ,  H01L51/0048 ,  H01L51/0541 ,  Y10S977/842 ,  Y10S977/845 ,  Y10S977/938

摘要： A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.

摘要翻译： 公开了一种形成具有受控直径和手性的单层壁厚（SWT）碳纳米管（CNT）晶体管的方法。 将光刻定义的单晶硅籽晶层转化为单晶碳化硅种子层。 在碳化硅的顶表面上形成单层石墨烯。 在存在含碳气体和金属催化剂原子的情况下，从石墨烯层生长SWT CNT晶体管体。 在碳化硅种子层的每一端的硅化源极和漏极区域在CNT形成期间提供催化剂金属原子。 SWT CNT的直径由图案种子层的宽度确定。 栅极电介质层上的共形淀积栅介质层和晶体管栅极完成了CNT晶体管。 还公开了具有多个CNT体，分离栅极和不同直径的CNT晶体管。