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    Method of making stackable layers containing encapsulated integrated circuit chips with one or more overlaying interconnect layers
    2.
    发明授权
    Method of making stackable layers containing encapsulated integrated circuit chips with one or more overlaying interconnect layers 有权
    制造包含具有一个或多个覆盖互连层的封装集成电路芯片的可堆叠层的方法

    公开(公告)号：US06797537B2

    公开(公告)日：2004-09-28

    申请号：US09938686

    申请日：2001-10-30

    申请人： Angel Antonio Pepe ,  James Satsuo Yamaguchi

    发明人： Angel Antonio Pepe ,  James Satsuo Yamaguchi

    IPC分类号： H01L2144

    CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/5388 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/1433 ,  H01L2924/18161

    摘要： A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.

    摘要翻译： 通过与预先形成的集成电路芯片分开形成互连组件，预先形成的集成电路芯片被封装到电子封装中。 如果互连组件测试良好，则它连接到准备好的集成电路芯片。 互连组件被翻转接合到芯片。 互连组件和芯片被钝化或封装成整体结构以提供电子封装。 在互连层中限定至少一个测试焊盘，该测试焊盘可以被访问并电连接在测试焊盘的相对侧上。 芯片底部填充有绝缘材料，以去除芯片和互连组件之间的所有空隙。 然后将集成电路芯片变薄。 访问测试板以测试芯片。 多个互连组件和芯片结合在一起以形成相应的多个电子封装。

    Stack of multilayer modules with heat-focusing metal layer
    4.
    发明授权
    Stack of multilayer modules with heat-focusing metal layer 有权
    堆叠具有热聚焦金属层的多层模块

    公开(公告)号：US06560109B2

    公开(公告)日：2003-05-06

    申请号：US09949024

    申请日：2001-09-07

    申请人： James Satsuo Yamaguchi ,  Angel Antonio Pepe ,  Volkan H. Ozguz ,  Andrew Nelson Camien

    发明人： James Satsuo Yamaguchi ,  Angel Antonio Pepe ,  Volkan H. Ozguz ,  Andrew Nelson Camien

    IPC分类号： H05K720

    CPC分类号： H05K3/0097 ,  H01L23/3735 ,  H01L23/3737 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1023 ,  H01L2225/1064 ,  H05K3/0052 ,  H05K3/403 ,  H05K2201/0129 ,  H05K2203/1105 ,  H05K2203/1536 ,  H05K2203/167

    摘要： A stack of multilayer modules has a segmentation layer disposed between neighboring multilayer modules. The segmentation layer facilitates the separation of neighboring multilayer modules. The stack of multilayer modules includes a first multilayer module and a second multilayer module. Each multilayer module includes a plurality of active layers each comprising a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The second multilayer module is disposed to be neighboring the first multilayer module with at least one segmentation layer between the first and second multilayer modules. The segmentation layer includes a metal layer and at least one thermoplastic adhesive layer. When heat is applied, the metal layer conducts heat to the thermoplastic adhesive layer.

    摘要翻译： 一叠多层模块具有设置在相邻多层模块之间的分割层。 分割层有助于相邻多层模块的分离。 多层模块的堆叠包括第一多层模块和第二多层模块。 每个多层模块包括多个有源层，每个有源层包括衬底，至少一个电子元件和多个导电迹线。 第二多层模块被布置为与第一多层模块相邻，在第一和第二多层模块之间具有至少一个分割层。 分割层包括金属层和至少一个热塑性粘合剂层。 当施加热量时，金属层将热量传导到热塑性粘合剂层。

    Stackable layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers
    5.
    发明授权
    Stackable layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers 有权
    包含具有一个或多个上覆互连层的封装集成电路芯片的可堆叠层

    公开(公告)号：US06784547B2

    公开(公告)日：2004-08-31

    申请号：US10302680

    申请日：2002-11-21

    申请人： Angel Antonio Pepe ,  James Satsuo Yamaguchi

    发明人： Angel Antonio Pepe ,  James Satsuo Yamaguchi

    IPC分类号： H01L2348

    CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/5388 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/1433 ,  H01L2924/18161

    摘要： A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.

    摘要翻译： 通过与预先形成的集成电路芯片分开形成互连组件，预先形成的集成电路芯片被封装到电子封装中。 如果互连组件测试良好，则它连接到准备好的集成电路芯片。 互连组件被翻转接合到芯片。 互连组件和芯片被钝化或封装成整体结构以提供电子封装。 在互连层中限定至少一个测试焊盘，该测试焊盘可以被访问并电连接在测试焊盘的相对侧上。 芯片底部填充有绝缘材料，以去除芯片和互连组件之间的所有空隙。 然后将集成电路芯片变薄。 访问测试板来测试芯片。 多个互连组件和芯片结合在一起以形成相应的多个电子封装。