公开(公告)号：US06717061B2

公开(公告)日：2004-04-06

申请号：US09949512

申请日：2001-09-07

申请人： James Satsuo Yamaguchi ,  Angel Antonio Pepe ,  Volkan H. Ozguz ,  Andrew Nelson Camien

发明人： James Satsuo Yamaguchi ,  Angel Antonio Pepe ,  Volkan H. Ozguz ,  Andrew Nelson Camien

IPC分类号： H05K103

CPC分类号： H05K3/0097 ,  H01L23/3735 ,  H01L23/3737 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K3/403 ,  H05K2201/0129 ,  H05K2203/1105 ,  H05K2203/1536 ,  H05K2203/167 ,  Y10T428/12569 ,  Y10T428/24917 ,  H01L2924/00

摘要： Each multilayer module of a plurality of multilayer modules has a plurality of layers wherein each layer has a substrate therein. The plurality of multilayer modules includes a first multilayer module including a first layer and a second multilayer module including a second layer each having a top side and bottom side. The first layer and second layer each includes a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The plurality of multilayer modules further includes a heat-separating layer disposed between the top side of the first layer and the bottom side of the second layer. The first multilayer module is adhered to the second multilayer module and the first multilayer module can be detached from the second multilayer module by applying heat to the heat-separating layer.

摘要翻译： 多个多层模块的每个多层模块具有多个层，其中每个层在其中具有衬底。 多个多层模块包括第一多层模块，该第一多层模块包括第一层和第二多层模块，该第二层模块包括第二层，每层具有顶侧和底侧。 第一层和第二层各自包括衬底，至少一个电子元件和多个导电迹线。 多个多层模块还包括设置在第一层的顶侧和第二层的底侧之间的热分离层。 第一多层模块粘附到第二多层模块，并且第一多层模块可以通过向热分离层施加热量而从第二多层模块分离。

公开(公告)号：US6117704A

公开(公告)日：2000-09-12

申请号：US282704

申请日：1999-03-31

申请人： James S. Yamaguchi ,  Volkan H. Ozguz ,  Andrew N. Camien

发明人： James S. Yamaguchi ,  Volkan H. Ozguz ,  Andrew N. Camien

IPC分类号： H01L21/56 ,  H01L21/98 ,  H01L25/10 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L24/18 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14

摘要： A method and structure are disclosed which involve the re-wafering of previously processed and tested IC chips. The chips are encapsulated in supporting non-conductive material in a neo-wafer, so that they may be further processed preparatory to dicing layer units from the neo-wafer, which layer units are ready for stacking in a three-dimensional electronic package. Although the layer areas are the same, different stacked layers may contain different sized IC chips, and a single layer may encapsulate a plurality of chips. Precision of location of the separate IC chips in the neo-wafer is insured by use of photo-patterning means to locate openings in the neo-wafer into which extend conductive bumps on the chips. The neo-wafer is preferably formed with separate cavities in which the chips are located before they are covered with the encapsulating material.

摘要翻译： 公开了涉及先前处理和测试的IC芯片的重新晶片化的方法和结构。 芯片被封装在新晶片中的支撑非导电材料中，使得它们可以被进一步加工成准备从新晶片切割层单元，该层单元准备好在三维电子封装中堆叠。 虽然层区域相同，但是不同的堆叠层可以包含不同尺寸的IC芯片，并且单层可以封装多个芯片。 通过使用光图案装置来确保新晶片中的单独的IC芯片的位置精度，以定位新晶圆中的开口，延伸到芯片上的导电凸起。 新晶片优选地形成有分离的空腔，其中芯片在它们被封装材料覆盖之前位于其中。

公开(公告)号：US07440449B2

公开(公告)日：2008-10-21

申请号：US10960712

申请日：2004-10-06

申请人： John C. Carson ,  Volkan H. Ozguz

发明人： John C. Carson ,  Volkan H. Ozguz

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L29/00 ,  H04L39/00

CPC分类号： G06T7/20 ,  G06T9/004 ,  H04L45/583 ,  H04L49/101 ,  H04L49/1507 ,  H04L49/25 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/357 ,  Y10S257/93

摘要： A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a second plurality of output ports (190) comprising: a first stack (140) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (142); a second stack (160) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer (113) containing at least one switching element circuit (162); and interconnecting circuitry (150) that connects the first stack (140) of IC layers to the second stack (160) of IC layers to form the compact multi-stage switching network. The stacks (140, 160) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection. Also contemplated are the use of superconducting IC switching circuits (142) and a suitable superconducting cooling housing (730), as permitted by the compact nature of the multi-stage switching network (100), in order to operate at high speed and low power.

摘要翻译： 紧凑型多级交换网络（100）以及包含这种多级交换网络的路由器（510），适用于将多个数据分组从第一多个输入端口（110）同时路由到第二个 多个输出端口（190）包括：彼此物理接触堆叠的IC开关层（113）的第一堆叠（140），每个IC开关层包含至少一个开关元件电路（142）; 叠层物理接触的IC开关层（113）的第二堆叠（160），每个IC开关层（113）包含至少一个开关元件电路（162）; 以及将IC层的第一堆叠（140）连接到IC层的第二堆叠（160）的互连电路（150），以形成紧凑的多级交换网络。 堆叠（140,160）优选以横向方式彼此配合，以便实现自然的全网状连接。 还考虑了如多级开关网络（100）的紧凑特性所允许的超导IC开关电路（142）和合适的超导冷却壳体（730）的使用，以便以高速和低功率运行 。

公开(公告)号：US06856167B2

公开(公告)日：2005-02-15

申请号：US10347038

申请日：2003-01-17

申请人： Volkan H. Ozguz ,  Randolph S. Carlson ,  Keith D. Gann ,  John P. Leon

发明人： Volkan H. Ozguz ,  Randolph S. Carlson ,  Keith D. Gann ,  John P. Leon

IPC分类号： G01R31/3185 ,  G06F9/38 ,  H03K19/177

CPC分类号： G01R31/318519 ,  G06F9/3802 ,  H01L2224/16227 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17796

摘要： A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as mXN where m is the number of word width bits per memory chip and N is the number of memory chips.

摘要翻译： 现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。 绝对最大字宽可以与mXN一样大，其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。

公开(公告)号：US07902879B2

公开(公告)日：2011-03-08

申请号：US12639625

申请日：2009-12-16

申请人： Volkan H. Ozguz ,  Randolph S. Carlson ,  Keith D. Gann ,  John Leon ,  W. Eric Boyd

发明人： Volkan H. Ozguz ,  Randolph S. Carlson ,  Keith D. Gann ,  John Leon ,  W. Eric Boyd

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： H03K19/1776 ,  G01R31/318519 ,  G06F9/3802 ,  H03K19/177 ,  H03K19/17792

摘要： A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

摘要翻译： 现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。 绝对最大字宽度可以与m * N一样大，其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。

公开(公告)号：US07649386B2

公开(公告)日：2010-01-19

申请号：US11897938

申请日：2007-08-31

申请人： Volkan H. Ozguz ,  Randolph S. Carlson ,  Keith D. Gann ,  John Leon ,  W. Eric Boyd

发明人： Volkan H. Ozguz ,  Randolph S. Carlson ,  Keith D. Gann ,  John Leon ,  W. Eric Boyd

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： H03K19/1776 ,  G01R31/318519 ,  G06F9/3802 ,  H03K19/177 ,  H03K19/17792

摘要： A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

摘要翻译： 现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。 绝对最大字宽度可以与m.times.N一样大m其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。

公开(公告)号：US07127807B2

公开(公告)日：2006-10-31

申请号：US10431914

申请日：2003-05-07

申请人： James Satsuo Yamaguchi ,  Angel Antonio Pepe ,  Volkan H. Ozguz ,  Andrew Nelson Camien

发明人： James Satsuo Yamaguchi ,  Angel Antonio Pepe ,  Volkan H. Ozguz ,  Andrew Nelson Camien

IPC分类号： H05K3/36 ,  B29C65/00 ,  H01L21/82

CPC分类号： H01L25/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K1/095 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0919 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T156/1089 ,  Y10T156/1092 ,  H01L2924/00

摘要： A method is disclosed for providing electrical connections to electronic elements within a multilayer module. The method includes providing first and second active layers having first and second edges, respectively. Each active layer includes a flexible, polymer substrate and at least one electronic element formed within the substrate. Electrically-conductive traces provide electrical connections from the first and second edges to the electronic elements. An adhesive is applied to at least one of a top surface of the first active layer and a bottom surface of the second active layer and the top surface of the first active layer is adhered to the bottom surface of the second active layer. The first edge and the second edge are aligned with each other thereby forming a side of the multilayer module. Electrically-conductive lines are applied along the side of the multilayer module to provide electrical connections to the traces.

摘要翻译： 公开了一种用于提供与多层模块内的电子元件的电连接的方法。 该方法包括分别提供具有第一和第二边缘的第一和第二有源层。 每个有源层包括柔性聚合物基底和形成在基底内的至少一个电子元件。 导电迹线提供从第一和第二边缘到电子元件的电连接。 将粘合剂施加到第一有源层的顶表面和第二有源层的底表面中的至少一个，并且第一有源层的顶表面粘附到第二有源层的底表面。 第一边缘和第二边缘彼此对准，从而形成多层模块的一侧。 沿着多层模块的侧面施加导电线以提供与迹线的电连接。

公开(公告)号：US5242707A

公开(公告)日：1993-09-07

申请号：US632033

申请日：1990-12-21

申请人： Sadik C. Esener ,  Sing H. Lee ,  Subramania Krishnakumar ,  Volkan H. Ozguz ,  Chi Fan

发明人： Sadik C. Esener ,  Sing H. Lee ,  Subramania Krishnakumar ,  Volkan H. Ozguz ,  Chi Fan

IPC分类号： C23C14/08 ,  C23C14/50 ,  G02F1/055 ,  H01L21/84

CPC分类号： C23C14/505 ,  C23C14/088 ,  G02F1/0551 ,  H01L21/84

摘要： A system and method are disclosed for producing electro-optic components with transparent, ferroelectric PLZT (perovskite) film characteristics, without lead diffusion. In particular, the fabrication of PLZT-on-sapphire electro-optic components for devices such as spatial light modulators, integrated infrared detectors, and optoelectronic integrated circuits is disclosed, permitting integration of such devices with semiconductor devices having the same substrate, such as silicon-on-sapphire circuits. The system comprises a PLZT film deposition apparatus, a silicon dioxide deposition apparatus, an annealing apparatus, and an optional plasma etching apparatus. During film deposition, material from a PLZT target (source) of suitable (9/65/35) composition is deposited on the substrate and is epitaxially grown on the R-plane (1102) of the substrate, forming a non-ferroelectric, pyrochloric film. The substrate and film are then placed in a silicon dioxide (SiO.sub.2) deposition chamber where SiO.sub.2 is deposited as an insulating layer covering (capping) the film. The substrate, with film and SiO.sub.2 layer, is then placed in an annealing apparatus, at a selected temperature above 550.degree. C. for a selected period of time, to transform the non-ferroelectric, pyrochloric film into a ferroelectric, perovskite film of (9/65/35) composition. The SiO.sub.2 layer may then be removed by conventional etching.

摘要翻译： 公开了一种用于生产具有透明的铁电PLZT（钙钛矿）膜特性的电光元件而不引线扩散的系统和方法。 特别地，公开了用于诸如空间光调制器，集成红外检测器和光电集成电路的器件的PLZT-蓝宝石电光元件的制造，允许这样的器件与具有相同衬底的半导体器件（诸如硅 - 蓝宝石电路。 该系统包括PLZT膜沉积设备，二氧化硅沉积设备，退火设备和可选的等离子体蚀刻设备。 在膜沉积期间，将来自适合（9/65/35）组成的PLZT靶（源）的材料沉积在衬底上并在衬底的R平面（1102）上外延生长，形成非铁电，高氯酸 电影。 然后将衬底和膜放置在二氧化硅（SiO 2）沉积室中，其中SiO 2沉积为覆盖（封盖）膜的绝缘层。 然后将具有膜和SiO 2层的衬底在选定的温度高于550℃的退火设备中放置一段选定的时间，以将非铁电的高氯酸盐膜转变成铁电体的钙钛矿膜（ 9/65/35）组成。 然后可以通过常规蚀刻去除SiO 2层。

公开(公告)号：US08074082B2

公开(公告)日：2011-12-06

申请号：US11248659

申请日：2005-10-11

申请人： Volkan H. Ozguz ,  John Leon

发明人： Volkan H. Ozguz ,  John Leon

IPC分类号： G06F11/30 ,  G06F1/26

CPC分类号： H01L23/576 ,  G06F21/87 ,  H01L23/48 ,  H01L23/49816 ,  H01L25/0657 ,  H01L27/02 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

摘要： An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided for routing connections between the integrated circuit and the connection layer. Specifically, the configurable logic device is programmable to create logical circuits connecting at least one of the input/output connectors of the integrated circuit to at least one of the input/output connectors of the connection layer. Configuration information for programming the reconfigurable logic device is stored in a memory within the module.

摘要翻译： 提供防篡改模块，用于保护组合在模块中的集成电路的内容和功能。 防篡改模块被布置成具有多层的堆叠构造。 提供连接层将模块连接到外部系统。 提供了一种用于在集成电路和连接层之间路由连接的可配置逻辑器件。 具体地，可配置逻辑器件是可编程的，以创建将集成电路的至少一个输入/输出连接器连接到连接层的至少一个输入/输出连接器的逻辑电路。 用于编程可重构逻辑器件的配置信息存储在模块内的存储器中。

公开(公告)号：US20100148822A1

公开(公告)日：2010-06-17

申请号：US12639625

申请日：2009-12-16

申请人： Volkan H. Ozguz ,  Randolph S. Carlson ,  Keith D. Gann ,  John Leon ,  W. Eric Boyd

发明人： Volkan H. Ozguz ,  Randolph S. Carlson ,  Keith D. Gann ,  John Leon ,  W. Eric Boyd

IPC分类号： H03K19/00

CPC分类号： H03K19/1776 ,  G01R31/318519 ,  G06F9/3802 ,  H03K19/177 ,  H03K19/17792

摘要： A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

摘要翻译： 现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。 绝对最大字宽度可以与m * N一样大，其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。