摘要:
An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region.
摘要:
A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.
摘要:
A method is described for forming gate structures with different metals on a single substrate. A thin semiconductor layer (26) is formed over gate dielectric (24) and patterned to be present in a first region (16) not a second region (18). Then, metal (30) is deposited and patterned to be present in the second region not the first. Then, a fully suicided gate process is carried out to result in a fully suicided gate structure in the first region and a gate structure in the second region including the fully suicided gate structure above the deposited metal (30).
摘要:
A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.
摘要:
A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the second gate facing the fin being formed of a metal silicide compound. The different compositions of the two gates provide different respective work functions to reduce short channel effects.
摘要:
A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spartial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.
摘要:
A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the second gate facing the fin being formed of a metal suicide compound. The different compositions of the two gates provide different respective work functions to reduce short channel effects.
摘要:
A silicon on insulator device has a silicon layer (10) over a buried insulating layer (12). A nickel layer is deposited over a gate (16), on sidewall spacers (22) on the sides of the gate (16), and in a cavity on both sides of the gate (16) in the silicon layer (10). A doped amorphous silicon layer fills the cavity. Annealing then takes place which forms polysilicon (40) over the sidewall spacers (22) and gate (16), but where the nickel is adjacent to single crystal silicon (10) a layer of NiSi (44) migrates to the surface leaving doped single crystal silicon (42) behind, forming in one step a source, drain, and source and drain contacts.
摘要:
The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semi-conductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2). According to the invention above the level of the metal silicide region (3) an insulating layer (5) is formed which is provided with an opening (6), the low-crystallinity silicon region (4) is deposited in the opening (6) and on top of the insulating layer (5), the part (4A, 4B) of the low-crystallinity silicon region (4) on top of the insulating layer (5) is removed by a planarization process after which the epitaxial silicon region (2) is formed. In this way an epitaxial silicon region (2), preferably a nano wire (2), is simply obtained that is provided with a metal silicide contact (region) in a self-aligned manner and that can form a part of semiconductor element (E) like a transistor.